2018
Dominic Oehlert SS,
Falk H.
Compiler-Based Extraction of Event Arrival Functions for Real-Time Systems Analysis.. In:
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Barcelona / Spain:
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Gianluca Martino HR,
Fey G.
Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems.. In:
In Proceedings of International Workshop on Logic & Synthesis (IWLS).
San Francisco / USA:
2018 Jul..
Görschwin Fey JR,
Riener H.
Design Understanding: From Logic to Specification.. In:
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Riener H,
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Mining Latency Guarantees for RTL Designs.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2018.
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Hollstein T,
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Software-Level TMR Approach for On-Board Data Processing in Space Applications.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2018.
Zimmermann K.
Computations in Stochastic Acceptors..
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Zimmermann K.
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Kateryna Muts AL,
Falk H.
Multi-Objective Optimization for the Compiler of Hard Real-Time Systems.. In:
In Proceedings of the 23rd International Symposium on Mathematical Programming (ISMP).
Bordeaux / France:
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2017
Luppold A,
Falk H.
Schedulability-Aware SPM Allocation for Preemptive Hard Real-Time Systems with Arbitrary Activation Patterns.. In:
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Lausanne / Switzerland:
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Dominic Oehlert AL,
Falk H.
Bus-aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems.. In:
In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS).
Dubrovnik / Croatia:
2017 Jun..
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Eberle Rambo SS,
Ernst R.
Designing Networks-on-Chip for High Assurance Real-Time Systems.. In:
In Proceedings of the International Symposium on Dependable computing (PRDC).
Christchurch / New Zealand:
2017 Jan..
Aydos G,
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Empirical Results on Parity-based Soft Error Detection with Software-based Retry..
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TODO
TODO
Riener H,
Fey G.
Computing Exact Fault Candidates Incrementally.. In:
Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
2017.
Riener H,
Koenighofer R,
Fey G,
Bloem R.
SMT-Based CPS Parameter Synthesis.. In:
Applied Verification for Continuous and Hybrid Systems (ARCH).
2017.
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Riener H,
Ehlers R,
Fey G.
CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification.. In:
ASP Design Automation Conference (ASPDAC).
2017.
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Riener H,
Ehlers R,
Fey G.
Counterexample-Guided EF Synthesis of Boolean Functions.. In:
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2017.
Malburg J,
Riener H,
Fey G.
Mining Latency Guarantees for RT-level Designs.. In:
Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
2017.
Malburg J,
Flenker T,
Fey G.
Property Mining using Dynamic Dependency Graphs.. In:
ASP Design Automation Conference (ASPDAC).
2017.
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Zimmermann K.
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Meß J,
Schmidt R,
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IEEE Aerospace Conference (AEROCONF).
2017.
Thole N,
Fey G.
Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2017.
Peter Marwedel ,
Neugebauer O.
Memory-Aware Optimization of Embedded Software for Multiple Objectives.. In:
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Schmidt R,
Garcia-Ortiz A,
Fey G.
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Avramenko S,
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Mapping Abstract and Concrete Hardware Models for Design Understanding.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
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Malburg J,
Fey G,
Avramenko S,
Violante M,
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Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.. In:
IEEE Annual Symposium on VLSI (ISVLSI).
2017.
2016
Adam Kostrzewa SS,
Ernst R.
Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chips.. In:
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Brest / France:
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Adam Kostrzewa SS,
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Safe and Dynamic Traffic Rate Control for Networks-on-Chips.. In:
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Nara / Japan:
2016 Aug..
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Adam Kostrzewa SS,
Ernst R.
Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network.. In:
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Pittsburgh / USA:
2016 Oct..
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Adam Kostrzewa SS,
Ernst R.
Slack-based resource arbitration for real-time Networks-on-Chip.. In:
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Dresden / Germany:
2016 Jan..
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Adam Kostrzewa LE,
Ernst R.
Dynamic admission control for real-time networks-on-chips.. In:
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2016 Jan..
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Andreas Becher SW,
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A LUT-Based Approximate Adder.. In:
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Arno Luppold CK,
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Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems.. In:
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St. Goar / Germany:
2016 May.
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Daniel Ziener JV,
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FPGA-Based Dynamically Reconfigurable SQL Query Processing..
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Dirk Koch DZ,
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FPGA versus Software Programming: Why, When, and How?.. In:
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2016 Jun..
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Dirk Koch FH,
Ziener D.
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2016 Jun..
[DOI]
Dominic Oehlert AL,
Falk H.
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St. Goar / Germany:
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Eberle Rambo SS,
Ernst R.
Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip.. In:
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2016 Jan..
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2016.
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Aydos G,
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TODO
TODO
Heiko Falk PW,
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TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research.. In:
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metaSMT: Focus On Your Application And Not On Solver Integration..
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Malburg J,
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Debugging hardware designs using dynamic dependency graphs..
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Malburg J,
Flenker T,
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Generating Good Properties from a Small Number of Use Cases.. In:
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2016.
Meß J,
Schmidt R,
Fey G,
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On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms.. In:
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2016.
Jorge Echavaria JT,
Ziener D.
FAU: Fast Approximate Adder Units on LUT-Based FPGAs.. In:
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Xi'an / China:
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Zimmermann K.
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Thole N,
Riener H,
Fey G.
Equivalence Checking on ESL Utilizing A Priori Knowledge.. In:
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2016.
Thole N,
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A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.. In:
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2016.
Krafczyk N,
Riener H,
Fey G.
WCET Overapproximation for Software in the Context of a Cyber-Physical System.. In:
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Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables.. In:
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On the robustness of compression algorithms for space applications.. In:
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2016.
Posewsky T,
Ziener D.
Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing.. In:
In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig).
Cancun / Mexico:
2016 Dec..
Flenker T,
Fey G.
Matching Abstract and Concrete Hardware Models for Design Understanding.. In:
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2016.
Wolfgang Büter DO,
García-Ortiz A.
ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition.. In:
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2015
Andreas Becher KM,
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A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering.. In:
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Andreas Becher DZ,
Teich J.
Approximate Adder Structures on FPGAs.. In:
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Paderborn / Germany:
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Luppold A,
Falk H.
Schedulability aware WCET-Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems.. In:
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Luppold A,
Falk H.
Code Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems.. In:
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Auckland / New Zealand:
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Che-Wei Chang TK,
Falk H.
Real-Time Task Scheduling on Island-Based Multi-Core Platforms..
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TODO
Aydos G,
Fey G.
Empirical Results on Parity-based Soft Error Detection with Software-based Retry.. In:
IEEE Nordic Circuits and Systems Conference (NORCAS).
2015.
Riener H,
Thomsen MK,
Fey G.
Execution Tracing of C Code for Formal Analysis (Extended Abstract).. In:
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2015.
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Riener H,
Ehlers R,
Fey G.
Path-Based Program Repair.. In:
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2015.
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Martinez J,
Malburg J,
Ziadi T,
Fey G.
Towards analysing feature locations through testing traces with BUT4Reuse.. In:
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2015.
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Dehbashi M,
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Thole N,
Fey G,
Garcia-Ortiz A.
Conservatively Analyzing Transient Faults.. In:
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2015.
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Thole N,
Fey G,
Garcia-Ortiz A.
Analyzing an SET at Gate Level using a Conservative Approach.. In:
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2015.
Thole N,
Riener H,
Fey G.
Equivalence Checking on System Level using A Priori Knowledge.. In:
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2015.
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Flenker T,
Sülflow A,
Fey G.
Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation.. In:
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2015.
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Ytterdal T,
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Chairs G,
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European Conference on Circuit Theory and Design (ECCTD).
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