Institute of Embedded Systems

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2014

Malburg J, Krafczyk N, Fey G. Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2014.
Borchers K, Fey G, Luedtke D. Automatic Performance Tracking of a SpaceWire Network.. In: International SpaceWire Conference. 2014.
Zimmermann K. Computability Theory.. 4. ed. Hamburg University of Technology; 2014 Jul..      [DOI] 
Dehbashi M, Fey G. Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms.. In: GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ). 2014.
Dehbashi M, Fey G. SAT-Based Speedpath Debugging Using Waveforms.. In: IEEE European Test Symposium (ETS). 2014. p. 63-68.
Dehbashi M, Fey G. Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs.. In: Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP). 2014. p. 400-404.      [DOI] 
Dehbashi M, Fey G. Debug Automation for Synchronization Bugs at RTL.. In: VLSI Design Conference. 2014. p. 44-49.      [DOI] 
Hanif MK. Mapping Dynamic Programming Algorithms on Graphics Processing Units. [Ph.D. Thesis.]. Hamburg / Germany: Hamburg University of Technology; 2014 Jul..      [DOI] 
Dück N, Zimmermann K. Gröbner bases for perfect binary codes.. International Journal of Pure and Applied Mathematics (IJPAM).. 2014 Feb.; 91.((2),):155-167.      [DOI] 
Dück N, Zimmermann K. Singleton codes.. International Journal of Pure and Applied Mathematics (IJPAM).. 2014 Jan.; 91.((3),):273-290.      [DOI] 
Dück N, Zimmermann K. Heuristic decoding of linear codes using commutative algebra.. Designs, Codes and Cryptography (DCC).. 2014 Jul.; 76.((1),):23-35.      [DOI] 
Dück N, Zimmermann K. Vector space bases for the homogeneous parts in homogeneous ideals and graded modules over a polynomial ring.. International Journal of Pure and Applied Mathematics (IJPAM).. 2014 Jun.; 93.((6),):835-844.      [DOI] 
Nicolas Roeser AL, Falk H. Multi-Criteria Optimization of Hard Real-Time Systems.. In: In Proceedings of the 8th Junior Researcher Workshop on Real-Time Computing (JRWRTC). Versailles / France: 2014 Oct.. p. 49-52.
Thole N, Fey G. Equivalence Checking on System Level using Stepwise Induction.. In: ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). 2014. p. 197-200.
Philip Axer RW, Yi W. Building Timing Predictable Embedded Systems.. ACM Transactions on Embedded Computing Systems (TECS).. 2014 Feb.; 13.((4),):      [DOI] 
Eggersglüß S, Fey G, Polian I. Test digitaler Schaltkreise.. De Gruyter Oldenbourg; 2014.
Sudipta Chattopadhyay PM, Falk H. A Unified WCET Analysis Framework for Multicore Platforms.. ACM Transactions on Embedded Computing Systems (TECS).. 2014 Jul.; 13.((4s),):      [DOI] 
Timon Kelter SC, Roychoudhury A. Static analysis of multi-core TDMA resource arbitration delays.. the International Journal of Time-Critical Computing Systems (Real-Time Systems).. 2014 Mar.; 50.((2),):185-229.      [DOI] 

2013

Finder A, Witte J, Fey G. Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2013. p. 60-65.
Arno Luppold HF, Slomka F. A New Concept for System-Level Design of Runtime Reconfigurable Real-Time Systems.. the ACM SIGBED Review.. 2013 Dec.; 10.((4),):57-60.      [DOI] 
Arno Luppold HF, Slomka F. A New Concept for System-Level Design of Runtime Reconfigurable Real-Time Systems.. In: In Proceedings of the 5th Workshop on Adaptive and Reconfigurable Embedded Systems (APRES). Philadelphia / USA: 2013 Apr..
Che-Wei Chang TK, Falk H. Real-Time Partitioned Scheduling on Multi-Core Systems with Local and Global Memories.. In: In Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC). Yokohama / Japan: 2013 Jan.. p. 467-472.      [DOI] 
Große D, Fey G, Drechsler R. Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis.. Electronic Communications of the EASST.. 2013; 13 pages.      [DOI] 
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Riener H, Fey G. Yet a Better Error Explanation Algorithm (Extended Abstract).. In: ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). 2013. p. 193-194.
Riener H, Frehse S, Fey G. Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis.. In: Design, Automation and Test in Europe (DATE). 2013. p. 939-942.
Jan C. Kleinsorge HF, Marwedel P. Simple Analysis of Partial Worst-case Execution Paths on General Control Flow Graphs.. In: In Proceedings of the International Conference on Embedded Software (EMSOFT). Montreal / Canada: 2013 Oct..      [DOI] 
Malburg J, Finder A, Fey G. Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns.. In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE). 2013. p. 59-66.
Malburg J, Finder A, Fey G. Tuning Dynamic Data Flow Analysis to Support Design Understanding.. In: Design, Automation and Test in Europe (DATE). 2013. p. 1179-1184.
Zimmermann K. Computability Theory.. 3. ed. Hamburg University of Technology; 2013 Jul..      [DOI] 
Sekanina L, Fey G, Raik J, Aunet S, (editors) RR. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2013.
Dehbashi M, Sülflow A, Fey G. Automated Design Debugging in a Testbench-Based Verification Environment.. Microprocessors and Microsystems (MICPRO).. 2013; 206-217.
Dehbashi M, Fey G. Debug Automation for Logic Circuits Under Timing Variations.. IEEE Design and Test of Computers (DT).. 2013; 60-69.      [DOI] 
Dehbashi M, Fey G. Efficient Automated Speedpath Debugging.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2013. p. 48-53.
Dehbashi M, Fey G. Towards Debug Automation for Timing Bugs at RTL.. In: GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ). 2013.
Dück N, Zimmermann K. Universal Gröbner bases for linear codes.. International Journal of Pure and Applied Mathematics (IJPAM).. 2013 Jul.; 86.((2),):345-358.      [DOI] 
Dück N, Zimmermann K. Computing generating sets for quaternary codes using Gröbner bases.. International Journal of Pure and Applied Mathematics (IJPAM).. 2013 Apr.; 84.((1),):99-109.      [DOI] 
Aitken R, Fey G, Kalbarczyk ZT, Reichenbach F, Reorda MS. Reliability Analysis Reloaded: How Will We Survive?.. In: Design, Automation and Test in Europe (DATE). 2013. p. 358-367.
Torgasin S, Zimmermann K. An all-pairs shortest path algorithm for bipartite graphs.. Central European Journal of Computer Science (CEJCS).. 2013 Dec.; 3.((4),):149-157.      [DOI] 
Timon Kelter PM, Falk H. Evaluation of resource arbitration methods for multi-core real-time systems.. In: In Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis (WCET). Paris / France: 2013 Jul.. p. 1-10.      [DOI] 
Retter W. Topics in Abstract Order Geometry. [Ph.D. Thesis.]. Hamburg / Germany: Hamburg University of Technology; 2013 Sep..      [DOI] 

2012

Saleemi M. Coding Theory via Groebner Bases. [Ph.D. Thesis.]. Hamburg / Germany: Hamburg University of Technology; 2012 Oct..      [DOI] 
Hanif MK, Zimmermann K. Graphics card processing: accelerating profile-profile alignment.. Central European Journal of Computer Science (CEJCS).. 2012 Dec.; 2.((4),):367-388.      [DOI] 
Dück N, Zimmermann K. A variant of the Gröbner basis algorithm for computing Hilbert bases.. International Journal of Pure and Applied Mathematics (IJPAM).. 2012 Nov.; 81.((1),):145-155.
Dück N, Zimmermann K. Standard bases for linear codes.. International Journal of Pure and Applied Mathematics (IJPAM).. 2012 Oct.; 80.((3),):315-329.
Torres OMR. Neural Synchronization and Light-weight Cryptography in Embedded Systems. [Ph.D. Thesis.]. Hamburg / Germany: Hamburg University of Technology; 2012 Aug..      [DOI] 
Philip Axer RW, Yi W. Building Timing Predictable Embedded Systems.. Uppsala / Sweden: 2012 Jul.. Report No.: (#2012-013),.
Bloem R, Drechsler R, Fey G, Finder A, Hofferek G, Könighofer R, Raik J, Repinski U, Sülflow A. FoREnSiC - An Automatic Debugging Environment for C Programs.. In: IBM Haifa Verification Conference (HVC). 2012. p. 260-265.
Sascha Plazar JCK, Marwedel P. WCET-aware Static Locking of Instruction Caches.. In: In Proceedings of the International Symposium on Code Generation and Optimization (CGO). San Jose / USA: 2012 Apr.. p. 44-52.      [DOI] 
Frehse S, Fey G, Arbel E, Yorav K, Drechsler R. Complete and Effective Robustness Checking by Means of Interpolation.. In: Formal Methods in Computer-Aided Design (FMCAD). 2012. p. 82-90.
Frehse S, Riener H, Fey G. Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz.. In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE). 2012. p. 90-96.
Sudipta Chattopadhyay HF, Marwedel P. A Unified WCET Analysis Framework for Multi-core Platforms.. In: In Proceedings of the 18th Real-Time and Embedded Technology and Applications Symposium (RTAS). Beijing / China: 2012 Apr.. p. 99-108.      [DOI] 
Torgasin S. Graph-based Methods for the Design of DNA Computations. [Ph.D. Thesis.]. Hamburg / Germany: Hamburg University of Technology; 2012 Jan..      [DOI] 
Wolfgang Kramper RW, Zimmermann K. Analysis of swarm behavior using compound eye and neural network control.. Central European Journal of Computer Science (CEJCS).. 2012 Mar.; 2.((1),):16-32.      [DOI] 
Che-Wei Chang TK, Falk H. Partitioned Scheduling for Real-Time Tasks on Multiprocessor Embedded Systems with Programmable Shared SRAMs.. In: In Proceedings of the International Conference on Embedded Software (EMSOFT). Tampere / Finland: 2012 Oct.. p. 153-162.      [DOI] 
Finder A, Fey G. Evaluating Debugging Algorithms from a Qualitative Perspective.. In: System Specification and Design Languages - Selected Contributions from FDL 2010. IET; 2012. p. 21-36.
Fey G. Assessing System Vulnerability using Formal Verification Techniques.. In: Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS) - Revised Selected Papers. 2012. p. 47-56.
Fey G, Fujita M, Miskov-Zivanov N, Roy K, (editors) MSR. Verifying Reliability (Dagstuhl Seminar 12341).. Dagstuhl Reports.. 2012; 57-73.      [DOI] 
Fey G, Fujita M, Miskov-Zivanov N, Roy K, (Organizers) MSR. Verifying Reliability (Dagstuhl Seminar 12341).. Dagstuhl Reports.. 2012;
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Falk H, (Eds.) PM. Introduction to the Special Section on SCOPES'09.. ACM Transactions on Embedded Computing Systems (TECS).. 2012 Jun.; 11S.((1),):17:1-17:3.      [DOI] 
Falk H, (Eds.) WY. Proceedings of the 13th International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES).. Beijing / China: 2012 Jun..     [File] 
Heiko Falk BL, Petters SM. Code-Level Timing Analysis of Embedded Software.. In: In Proceedings of the International Conference on Embedded Software (EMSOFT). Tampere / Finland: 2012 Oct.. p. 163-164.      [DOI] 
Heiko Falk PM, Lokuciejewski P. Reconciling Compilation and Timing Analysis.. In: In S. Chakraborty and J. Eberspächer (Eds.), editors. Advances in Real-Time Systems. Springer; 2012 Mar.. p. 145-170.      [DOI] 
Riener H, Fey G. Model-Based Diagnosis versus Error Explanation.. In: ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE). 2012. p. 43-52.
Riener H, Fey G. Model-Based Diagnosis versus Error Explanation.. In: International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES). 2012.
Riener H, Fey G. FAUST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.. In: International SPIN Workshop on Model Checking of Software (SPIN). 2012. p. 234-240.
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Malburg J, Finder A, Fey G. Automated Feature Localization for Hardware Designs using Coverage Metrics.. In: Design Automation Conference (DAC). 2012. p. 941-946.
Malburg J, Finder A, Fey G. Automated Feature Localization for Hardware Designs using Coverage Metrics.. In: ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). 2012.
Zimmermann K. Computability Theory.. 2. ed. Hamburg University of Technology; 2012 Jul..      [DOI] 
Soeken M, Riener H, Wille R, Fey G, Drechsler R. Verification of Embedded Systems Using Modeling and Implementation Languages.. In: International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs). 2012. p. 67-72.
Dehbashi M, Fey G. Automated Debugging from Pre-Silicon to Post-Silicon.. In: GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ). 2012.
Dehbashi M, Fey G. Automated Post-Silicon Debugging of Failing Speedpaths.. In: Asian Test Symposium (ATS). 2012. p. 13-18.
Dehbashi M, Fey G. Application of Timing Variation Modeling to Speedpath Diagnosis.. In: System, Software, SoC and Silcon Debug Conference (S4D). 2012. p. 34-37.
Dehbashi M, Fey G. Automated Debugging from Pre-Silicon to Post-Silicon.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2012. p. 324-329.
Dehbashi M, Fey G, Roy K, Raghunathan A. On Modeling and Evaluation of Logic Circuits Under Timing Variations.. In: EUROMICRO Symposium on Digital System Design (DSD). 2012. p. 431-436.
Dehbashi M, Fey G, Roy K, Raghunathan A. Functional Analysis of Circuits Under Timing Variations.. In: edaWorkshop. 2012. p. 45-50.
Dehbashi M, Fey G, Roy K, Raghunathan A. Functional Analysis of Circuits Under Timing Variations.. In: IEEE European Test Symposium (ETS). 2012. p. 177.

2011

Finder A, Sülflow A, Fey G. Latency Analysis for Sequential Circuits.. In: GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ). 2011. p. 119-124.
Finder A, Sülflow A, Fey G. Latency Analysis for Sequential Circuits.. In: IEEE European Test Symposium (ETS). 2011. p. 129-134.      [DOI] 
Große D, Fey G, Drechsler R. Enhanced Formal Verification Flow for Circuits Integrating Debugging.. In: Design and Test Technology for Dependable Systems-on-Chip. Information Science Reference; 2011. p. 119-129.
Haedicke F, Frehse S, Fey G, Große D, Drechsler R. metaSMT: Focus on Your Application not on Solver Integration.. In: Int'l Workshop on Design and Implementation of Formal Tools and Systems (DIFTS). 2011. p. 22-29.
Fey G. Assessing System Vulnerability using Formal Verification Techniques.. In: Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS). 2011.
Fey G. Orchestrated Multi-Level Information Flow Analysis to Understand SoCs.. In: Design Automation Conference (DAC). 2011. p. 284-285.
Fey G, Sülflow A, Frehse S, Drechsler R. Effective Robustness Analysis using Bounded Model Checking Techniques.. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD).. 2011; 1239-1252.      [DOI] 
Falk H, Kotthaus H. WCET-driven Cache-aware Code Positioning.. In: In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Taipei / Taiwan: 2011 Oct.. p. 145-154.      [DOI] 
Heiko Falk NS, Schmoll F. WCET-aware Register Allocation based on Integer-Linear Programming.. In: In Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS). Porto / Portugal: 2011 Jul.. p. 13-22.      [DOI] 
Riener H, Bloem R, Fey G. Test Case Generation from Mutants using Model Checking Techniques.. In: Mutation. 2011. p. 388-397.
Jan C. Kleinsorge HF, Marwedel P. A Synergetic Approach to Accurate Analysis of Cache-Related Preemption Delay.. In: In Proceedings of the International Conference on Embedded Software (EMSOFT). Taipei / Taiwan: 2011 Oct.. p. 329-338.      [DOI] 
Zimmermann K. Computability Theory.. 1. ed. Hamburg University of Technology; 2011 Jul..      [DOI] 
Soeken M, Kühne U, Freibothe M, Fey G, Drechsler R. Towards Automatic Property Generation for the Formal Verification of Bus Bridges.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2011. p. 417-422.
Soeken M, Kühne U, Freibothe M, Fey G, Drechsler R. Towards Automatic Property Generation for the Formal Verification of Bus Bridges.. In: ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). 2011.
Dehbashi M, Sülflow A, Fey G. Automated Design Debugging in a Testbench-Based Verification Environment.. In: EUROMICRO Symposium on Digital System Design (DSD). 2011. p. 479-486.
Dehbashi M, Fey G. Automated Post-Silicon Debugging of Design Bugs.. In: System, Software, SoC and Silcon Debug Conference (S4D). 2011. p. 67-71.
Saleemi M, Zimmermann K. Groebner bases for linear codes over GF(4).. International Journal of Pure and Applied Mathematics (IJPAM).. 2011 Dec.; 73.((4),):435-442.
Paul Lokuciejewski PM, Thiele L. Approximating Pareto optimal compiler optimization sequences-a trade-off between WCET, ACET and code size.. Software: Practice and Experience.. 2011 Nov.; 41.((12),):1437-1458.      [DOI] 
Robert Leppert MS, Zimmermann K. Groebner bases for quaternary codes.. International Journal of Pure and Applied Mathematics (IJPAM).. 2011 Oct.; 71.((4),):595-608.
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