2007
Israel Marck Martinez-Perez ZI,
Zimmermann K.
Computational genes: a tool for molecular diagnosis and therapy of aberrant mutational phenotype..
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2007 Sep.;
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[DOI]
TODO
Paul Lokuciejewski MS,
Marwedel P.
Tighter WCET Estimates by Procedure Cloning.. In:
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2007 Jul..
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Paul Lokuciejewski PM,
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Robert Pyka HF,
Marwedel P.
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Drechsler R.
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2007.
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Wille R,
Fey G,
Drechsler R.
Building Free Binary Decision Diagrams Using SAT Solvers..
Facta Universitatis..
2007;
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Wille R,
Fey G,
Drechsler R.
Building Free Binary Decision Diagrams Using SAT Solvers.. In:
Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design.
2007.
Drechsler R,
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An Integrated Approach for Combining BDDs and SAT Provers..
Facta Universitatis..
2007;
415-436.
Kinder S,
Fey G,
Drechsler R.
Estimating the Quality of AND-EXOR Optimization Results.. In:
Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design.
2007.
Eggersglüß S,
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Fey G,
Drechsler R,
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Experimental Studies on SAT-based ATPG for Gate Delay Faults.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2007.
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Eggersglüß S,
Fey G,
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SAT-based ATPG for Path Delay Faults in Sequential Circuits.. In:
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2007.
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Eggersglüß S,
Fey G,
Drechsler R,
Glowatz A,
Hapke F,
Schloeffel J.
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.. In:
ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE).
2007.
p. 181-187.
2006
Ruttor A,
Volkmer M.
Theorie und Anwendungen von Tree Parity Machines für die Kryptographie.. In:
In Proceedings of Workshop über Kryptographie (Kryptowochenende 2006).
Mannheim / Germany:
2006 Jul..
p. 20-22.
Fey G.
Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques.
[Ph.D. Thesis.].
...;
2006.
Fey G,
Große D,
Drechsler R.
Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks.. In:
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2006.
p. 1225-1226.
Fey G,
Shi J,
Drechsler R.
Efficiency of multiple-valued encoding in SAT-based ATPG.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2006.
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Fey G,
Shi J,
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Efficiency of multiple-valued encoding in SAT-based ATPG.. In:
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2006.
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Fey G,
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SAT-based Calculation of Source Code Coverage for BMC.. In:
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2006.
p. 163-170.
Fey G,
Drechsler R.
Minimizing the Number of Paths in BDDs - Theory and Algorithm..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2006;
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Fey G,
Safarpour S,
Veneris A,
Drechsler R.
On the Relation Between Simulation-based and SAT-based Diagnosis.. In:
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2006.
p. 1139-1144.
Fey G,
Warode T,
Drechsler R.
Using Structural Learning Techniques in SAT-based ATPG.. In:
Int'l Workshop on Boolean Problems (IWSBP).
2006.
p. 63-69.
Falk H,
Schwarzer M.
Loop Nest Splitting for WCET-Optimization and Predictability Improvement.. In:
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Falk H,
Schwarzer M.
Loop Nest Splitting for WCET-Optimization and Predictability Improvement.. In:
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Dresden / Germany:
2006 Jul..
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Heiko Falk JW,
Schaefer A.
Use of a Bit-true Data Flow Analysis for Processor-Specific Source Code Optimization.. In:
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Heiko Falk PL,
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Heiko Falk PL,
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Dresden / Germany:
2006 Jul..
[DOI]
Israel Marck Martinez-Perez ZI,
Zimmermann K.
Solving the Maximum Clique Problem via DNA Hairpin Formation..
Hamburg / Germany:
2006 Dec..
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Report No.: (06.3),.
Israel Marck Martinez-Perez ZI,
Zimmermann K.
An Autonomous DNA Model for Stochastic Finite State Automata..
Hamburg / Germany:
2006 May.
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Israel Marck Martinez-Perez ZI,
Zimmermann K.
An Autonomous DNA Model for Finite State Automata..
Hamburg / Germany:
2006 May.
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Report No.: (06.1),.
Tyss K.
Generatoren für echte Zufallszahlen auf FPGAs für eingebettete Systeme.. In:
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Kassel / Germany:
2006 Sep..
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Zimmermann K.
Diskrete Mathematik..
Books on Demand;
2006 Aug..
Volkmer M.
On proving Completeness, Soundness and Security of Authenticated Tree Parity Machine Key Exchange.. In:
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Bochum / Germany:
2006 May.
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TODO
Volkmer M,
Wallner S.
Ein IP-Core Design für Schlüsselaustausch, Stromchiffre und Identifikation auf ressourcenbeschränkten Geräten.. In:
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Magdeburg / Germany:
2006 Feb..
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TODO
Drechsler R,
Fey G.
Automatic Test Pattern Generation.. In:
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Springer;
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Drechsler R,
Fey G,
Kinder S.
An Integrated Approach for Combining BDD and SAT Provers.. In:
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Sascha Mühlbach MV,
Wallner S.
Encrypted and Authenticated Communication via Tree-Parity Machines in AMBA Bus Systems.. In:
In Proceedings of Workshop über Kryptographie (4. Krypto-Tag).
Bochum / Germany:
2006 May.
p. 10.
Staber S,
Fey G,
Bloem R,
Drechsler R.
Automatic Fault Localization for Property Checking.. In:
IBM Haifa Verification Conference (HVC).
2006.
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2005
Breiter A,
Fey G,
Drechsler R.
Project-Based Learning in Student Teams in Computer Science Education..
Facta Universitatis..
2005;
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Saballus B.
Secure Group Communication in WLAN Ad-Hoc Networks with Tree Parity Machines.. In:
In Proceedings of Workshop über Kryptographie (2. Krypto-Tag).
Ulm / Germany:
2005 Mar..
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Fey G,
Drechsler R.
Efficient Hierarchical System Debugging for Property Checking.. In:
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS).
2005.
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Fey G,
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FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC..
Shaker;
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Falk H.
Control Flow driven Code Hoisting at the Source Code Level.. In:
In Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES).
San Jose / United States:
2005 Mar..
Israel Marck Martinez-Perez ZI,
Zimmermann K.
Biomolecular autonomous solution of the Hamiltonian path problem via hairpin formation..
International Journal of Bioinformatics Research and Applications (IJBRA)..
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Shi J,
Fey G,
Drechsler R.
Bridging Fault Testability of BDD Circuits.. In:
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2005.
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Shi J,
Fey G,
Drechsler R,
Glowatz A,
Schloeffel J,
Hapke F.
PASSAT: Efficient SAT-based Test Pattern Generation.. In:
IEEE Annual Symposium on VLSI (ISVLSI).
2005.
p. 212-217.
Shi J,
Fey G,
Drechsler R,
Glowatz A,
Schloeffel J,
Hapke F.
Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits.. In:
IEEE Int'l Conference on ASIC (ASICON).
2005.
Shi J,
Fey G,
Drechsler R,
Glowatz A,
Schloeffel J,
Hapke F.
PASSAT: Efficient SAT-based Test Pattern Generation.. In:
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS).
2005.
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Zimmermann K.
Solving constrained combinatorial optimization problems via importance sampling in the grand canonical ensemble..
Computer Physics Communications..
2005 Feb.;
165.((3),):243-259.
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Elssel K,
Zimmermann K.
Two New Nonlinear Binary Codes..
IEEE Transactions on Information Theory..
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Manish Verma HF,
Marwedel P.
Scratchpad Sharing Strategies for Multiprocess Embedded Systems: A First Approach.. In:
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Volkmer M,
Grewe F.
Runners, Starting Lines and Mutual Distances: On the Security of Tree Parity Machine Key Exchange.. In:
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Darmstadt / Germany:
2005 Sep..
p. 5.
Volkmer M,
Wallner S.
A Key Establishment IP-Core for Ubiquitous Computing.. In:
In Proceedings of 16th International Workshop on Database and Expert Systems Applications.
Copenhagen / Denmark:
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TODO
Volkmer M,
Wallner S.
Lightweight Key Exchange and Stream Cipher based solely on Tree Parity Machines.. In:
In Proceedings of the ECRYPT Workshop on RFID and Lightweight Crypto.
Graz / Austria:
2005 Jul..
Volkmer M,
Wallner S.
Tree parity machine rekeying architectures..
IEEE Transactions on Computers..
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Behroozi N.
Immediate Rekeying by Tree Parity Machines in a WLAN-System.. In:
In Proceedings of Workshop über Kryptographie (2. Krypto-Tag).
Ulm / Germany:
2005 Mar..
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Drechsler R,
Fey G,
Genz C,
Große D.
SyCE: An Integrated Environment for System Design in SystemC.. In:
IEEE Int'l Workshop on Rapid System Prototyping (RSP).
2005.
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Ebendt R,
Fey G,
Drechsler R.
Advanced BDD Optimization..
Springer;
2005.
Safarpour S,
Fey G,
Veneris A,
Drechsler R.
Utilizing Don't Care States in SAT-based Bounded Sequential Problems.. In:
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2005.
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Kinder S,
Fey G,
Drechsler R.
Controlling the Memory During Manipulation of Word-Level Decision Diagrams.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2005.
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2004
Schaumburg A.
Authentication within Tree Parity Machine Rekeying.. In:
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Mannheim / Germany:
2004 Dec..
p. 13.
Fey G,
Große D,
Cassens T,
Genz C,
Warode T,
Drechsler R.
ParSyC: An Efficient SystemC Parser.. In:
Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI).
2004.
p. 148-154.
Fey G,
Shi J,
Drechsler R.
BDD Circuit Optimization for Path Delay Fault Testability.. In:
EUROMICRO Symposium on Digital System Design (DSD).
2004.
p. 162-172.
Fey G,
Drechsler R.
Improving Simulation-Based Verification by Means of Formal Methods.. In:
ASP Design Automation Conference (ASPDAC).
2004.
p. 640-643.
Fey G,
Drechsler R.
Visualization of Diagnosis Results for Design Debugging.. In:
Internatinal Workshop on Post-Binary ULSI Systems (ULSIWS).
2004.
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Fey G,
Drechsler R,
Ciesielski M.
Algorithms for Taylor Expansion Diagrams.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2004.
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Falk H.
Source Code Optimization Techniques for Data Flow Dominated Embedded Software.
[Ph.D. Thesis.].
Dortmund / Germany:
University of Dortmund;
2004 Jun..
Falk H,
Verma M.
Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization.. In:
In Proceedings of the 8th International Workshop on Software & Compilers for Embedded Systems (SCOPES).
Amsterdam / The Netherlands:
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Falk H,
Marwedel P.
Source Code Optimization Techniques for Data Flow Dominated Embedded Software..
Kluwer Academic Publishers;
2004 Oct..
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Winkelmann K,
Trylus H,
Stoffel D,
Fey G.
Cost-efficient Block Verification for a UMTS Up-link Chip-rate Coprocessor.. In:
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2004.
p. 162-167.
Volkmer M,
Wallner S.
A Low-Cost Solution for Frequent Symmetric Key Exchange in Ad-hoc Networks.. In:
In Proceedings of the Workshop Mobile Ad-hoc Netzwerke (WMAN).
Ulm / Germany:
2004 Sep..
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Drechsler N,
Hilgemeier M,
Fey G,
Drechsler R.
Disjoint Sum of Product Minimization by Evolutionary Algorithms.. In:
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2004.
p. 198-207.
Drechsler R,
Fey G.
Design Understanding by Automatic Property Generation.. In:
Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI).
2004.
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Drechsler R,
Shi J,
Fey G.
Synthesis of Fully Testable Circuits from BDDs..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2004;
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Wolfgang Achtziger AP,
Zimmermann K.
Optimization and Parallelization of Loop Nests via Linear Vector-Valued Schedules..
Dortmund / Germany:
2004 Jun..
Report No.: (#264),.
2003
Große D,
Fey G,
Drechsler R.
Modeling Multi-Valued Circuits in SystemC.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2003.
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Fey G,
Shi J,
Drechsler R.
BDD Circuit Optimization for Path Delay Fault-Testability.. In:
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2003.
Fey G,
Drechsler R.
A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization.. In:
Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI).
2003.
p. 54-60.
Fey G,
Drechsler R.
Finding Good Counter-Examples to Aid Design Verification.. In:
ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE).
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Fey G,
Kinder S,
Drechsler R.
Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2003.
p. 361-366.
TODO
Falk H,
Marwedel P.
Control Flow driven Splitting of Loop Nests at the Source Code Level.. In:
In Proceedings of Design, Automation and Test in Europe (DATE).
Munich / Germany:
2003 Mar..
p. 410-415.
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Heiko Falk MM,
Leupers R.
High-level Control Flow Transformations for Performance Improvement of Address-Dominated Multimedia Applications.. In:
In Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI).
Hiroshima / Japan:
2003 Apr..
p. 338-344.
Heiko Falk PM,
Catthoor F.
Control Flow driven Splitting of Loop Nests at the Source Code Level.. In:
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Shi J,
Fey G,
Drechsler R.
BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.. In:
Asian Test Symposium (ATS).
2003.
p. 290-293.
Shi J,
Fey G,
Drechsler R.
BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.. In:
IEEE European Test Workshop (ETW).
2003.
p. 109-110.
Shi J,
Fey G,
Drechsler R.
Random Pattern Testability of Circuits Derived from BDDs.. In:
IEEE Workshop on RTL and High Level Testing (WRTLT).
2003.
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Zimmermann K.
A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins..
Journal of Signal Processing Systems..
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Zimmermann K.
An Introduction to Protein Informatics..
Kluwer Academic Publishers;
2003.
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Winkelmann K,
Trylus H,
Stoffel D,
Fey G.
Cost-efficient Formal Block Verification for ASIC Design.. In:
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Drechsler R,
Shi J,
Fey G.
MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits.. In:
Great Lakes Symp. VLSI (GLS).
2003.
p. 80-83.
2002
Fey G,
Drechsler R.
Utilizing BDDs for Disjoint SOP Minimization.. In:
IEEE Midwest Symposium on Circuits and Systems (MWSCAS).
2002.
p. 306-309.
Fey G,
Drechsler R.
Minimizing the Number of Paths in BDDs.. In:
Symposium on Integrated Circuits and Systems Design (SBCCI).
2002.
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Fey G,
Drechsler R.
Minimizing the Number of Paths in BDDs.. In:
Int'l Workshop on Boolean Problems (IWSBP).
2002.
Falk H.
Control Flow Optimization by Loop Nest Splitting at the Source Code Level..
Dortmund / Germany:
2002 Oct..
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Ritter J,
Fey G,
Molitor P.
SPIHT implemented in a XC4000 device.. In:
IEEE Midwest Symposium on Circuits and Systems (MWSCAS).
2002.
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