2011
Sascha Plazar HF,
Marwedel P.
WCET-driven Branch Prediction aware Code Positioning.. In:
In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).
Taipei / Taiwan:
2011 Oct..
p. 165-174.
[DOI]
Frehse S,
Haedicke F,
Diepenbeck M,
Fey G,
Drechsler R.
Hochoptimierter Ablauf zur Robustheitsprüfung.. In:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE).
2011.
p. 35-42.
Timon Kelter SC,
Roychoudhury A.
Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds.. In:
In Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS).
Porto / Portugal:
2011 Jul..
p. 3-12.
[DOI]
Timon Kelter SC,
Roychoudhury A.
Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds..
Dortmund / Germany:
2011 Jan..
Report No.: (#837),.
2010
Finder A,
Fey G.
Evaluating Debugging Algorithms from a Qualitative Perspective.. In:
Int'l Workshop on Boolean Problems (IWSBP).
2010.
Finder A,
Fey G.
Evaluating Debugging Algorithms from a Qualitative Perspective.. In:
Forum on Specification and Design Languages (FDL).
2010.
Sülflow A,
Fey G,
Drechsler R.
Bounded Fault Tolerance Checking (Invited Talk).. In:
Forum on Specification and Design Languages (FDL).
2010.
Sülflow A,
Fey G,
Drechsler R.
Using QBF to Increase Accuracy of SAT-Based Debugging.. In:
IEEE Int'l Symposium on Circuits and Systems (ISCAS).
2010.
p. 641-644.
Cem Savas Bassoy MY,
Zimmermann K.
Accelerating Scalar-Product Based Sequence Alignment using Graphics Processor Units..
Journal of Signal Processing Systems..
2010 Nov.;
61.((2),):117-125.
[DOI]
Haedicke F,
Alizadeh B,
Fey G,
Fujita M,
Drechsler R.
Polynomial Datapath Optimization using Constraint Solving and Formal Modelling.. In:
IEEE/ACM Int'l Conf. on CAD (ICCAD).
2010.
p. 756-761.
TODO
Fey G,
Sülflow A,
Drechsler R.
Towards Unifying Localization and Explanation for Automated Debugging.. In:
International Workshop on Microprocessor Test and Verification (MTV).
2010.
p. 3-8.
Fey G,
Sülflow A,
Frehse S,
Drechsler R.
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen..
it - Information Technology..
2010;
216-222.
Falk H,
Lokuciejewski P.
A compiler framework for the reduction of worst-case execution times..
the International Journal of Time-Critical Computing Systems (Real-Time Systems)..
2010 Oct.;
46.((2),):251-300.
[DOI]
Israel Marck Martinez-Perez MW,
Zimmermann K.
Bioinspired Parallel Algorithms for Maximum Clique Problem on FPGA Architectures..
Journal of Signal Processing Systems..
2010 Feb.;
58.((2),):117-124.
[DOI]
Zimmermann K.
Und, wie hoch ist Ihre Erdös-Zahl?..
Spektrum Magazin..
2010;
Saleemi M,
Zimmermann K.
From ideals in polynomial rings to linear codes using Groebner bases..
International Journal of Pure and Applied Mathematics (IJPAM)..
2010 Dec.;
65.((1),):41-54.
Saleemi M,
Zimmermann K.
Groebner bases for linear codes..
International Journal of Pure and Applied Mathematics (IJPAM)..
2010 Aug.;
62.((4),):481-491.
Saleemi M,
Zimmermann K.
Linear codes as binomial ideals..
International Journal of Pure and Applied Mathematics (IJPAM)..
2010 Jun.;
61.((2),):147-156.
Saleemi M,
Zimmermann K.
Groebner bases for a class of ideals in commutative polynomial rings..
International Journal of Pure and Applied Mathematics (IJPAM)..
2010 Feb.;
58.((1),):1-9.
Reyes OM,
Zimmermann K.
Permutation parity machines for neural cryptography..
Physical Review E..
2010 Jun.;
81.((6),):
[DOI]
Paul Lokuciejewski PM,
Thiele L.
Multi-Objective Exploration of Compiler Optimizations for Real-Time Systems.. In:
In Proceedings of the 13th International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC).
Carmona / Spain:
2010 May.
p. 115-122.
[DOI]
TODO
TODO
Frehse S,
Fey G.
Kompositionelle Formale Robustheitsprüfung.. In:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE).
2010.
p. 73-74.
Frehse S,
Fey G,
Sülflow A,
Drechsler R.
RobuCheck: A Robustness Checker for Digital Circuits.. In:
EUROMICRO Symposium on Digital System Design (DSD).
2010.
p. 226-231.
Frehse S,
Fey G,
Sülflow A,
Drechsler R.
RobuCheck: A Robustness Checker for Digital Circuits.. In:
Workshop on Dynamic Aspects in Dependability Model for Fault-Tolerant Systems (DYADEM-FTS).
2010.
p. 37-38.
Frehse S,
Fey G,
Drechsler R.
A Better-Than-Worst-Case Robustness Measure.. In:
Int'l Test Conference (ITC).
2010.
Frehse S,
Fey G,
Drechsler R.
A Better-Than-Worst-Case Robustness Measure.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2010.
p. 78-83.
Frehse S,
Fey G,
Drechsler R.
A Better-Than-Worst-Case Robustness Measure.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2010.
p. 19-24.
Eggersglüß S,
Fey G,
Glowatz A,
Hapke F,
Schloeffel J,
Drechsler R.
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics..
Journal of Electronic Testing: Theory and Applications (JETTA)..
2010;
307-322.
Torgasin S,
Zimmermann K.
Algorithm for thermodynamically based prediction of DNA/DNA crosshybridization..
International Journal of Bioinformatics Research and Applications (IJBRA)..
2010;
6.((1),):82-97.
Kramper W.
Simulation von Schwarmverhalten..
Mensch & Buch;
2010 Apr..
2009
Sülflow A,
Fey G,
Braunstein C,
Kühne U,
Drechsler R.
Increasing the Accuracy of SAT-based Debugging.. In:
Design, Automation and Test in Europe (DATE).
2009.
p. 1326-1331.
Sülflow A,
Fey G,
Braunstein C,
Kühne U,
Drechsler R.
Increasing the Accuracy of SAT-based Debugging.. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
2009.
Sülflow A,
Fey G,
Drechsler R.
Using QBF to Increase Accuracy of SAT-based Debugging.. In:
Workshop on Constraints in Formal Verification (CFV).
2009.
Sülflow A,
Wille R,
Fey G,
Drechsler R.
Evaluation of Cardinality Constraints on SMT-based Debugging.. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2009.
p. 298-303.
Sülflow A,
Frehse S,
Fey G,
Drechsler R.
Anwendungsbezogene Analyse der Robustheit von digitalen Schaltungen.. In:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE).
2009.
p. 45-52.
Sülflow A,
Kühne U,
Fey G,
Große D,
Drechsler R.
WoLFram - A Word Level Framework for Formal Verification.. In:
IEEE/IFIP Int'l Symposium on Rapid System Prototyping (RSP).
2009.
p. 11-17.
TODO
Rogin F,
Klotz T,
Fey G,
Drechsler R,
Rülke S.
Advanced Verification by Automatic Property Generation..
IET Computers and Digital Techniques..
2009;
338-353.
Fey G.
Deterministic Algorithms for ATPG under Leakage Constraints.. In:
Asian Test Symposium (ATS).
2009.
p. 313-316.
Fey G.
Algorithms for ATPG under Leakage Constraints.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2009.
p. 91-96.
Fey G,
Sülflow A,
Drechsler R.
Computing Bounds for Fault Tolerance using Formal Techniques.. In:
Design Automation Conference (DAC).
2009.
p. 190-195.
Falk H.
WCET-aware Register Allocation based on Graph Coloring.. In:
In Proceedings of the 46th Design Automation Conference (DAC).
San Francisco / USA:
2009 Jul..
p. 726-731.
[DOI]
TODO
(Ed.) HF.
Proceedings of the 12th International Workshop on Software & Compilers for Embedded Systems (SCOPES)..
Nice / France:
ACM;
2009 Apr..
[File]
Falk H,
Kleinsorge JC.
Optimal Static WCET-aware Scratchpad Allocation of Program Code.. In:
In Proceedings of the 46th Design Automation Conference (DAC).
San Francisco / USA:
2009 Jul..
p. 732-737.
[DOI]
Martinez-Perez IM,
Zimmermann K.
Parallel bioinspired algorithms for NP complete graph problems..
Journal of Parallel and Distributed Computing (JPDC)..
2009 Mar.;
69.((3),):221-229.
[DOI]
Israel Marck Martinez-Perez KZ,
Ignatova Z.
An autonomous DNA model for finite state automata..
International Journal of Bioinformatics Research and Applications (IJBRA)..
2009;
5.((1),):81-96.
[DOI]
Israel Marck Martinez-Perez ZI,
Zimmermann K.
Exploiting the Features of the Finite State Automata for Biomolecular Computing..
Journal on Recent Patents on DNA & Gene Sequences..
2009;
3.((2),):130-138.
[DOI]
Torres OMR,
Zimmermann K.
Key exchange protocol using permutation parity machines.. In:
In Proceedings of the International Joint Conference on Computational Intelligence (IJCCI).
Madeira / Portugal:
2009 Oct..
p. 496-501.
Oscar Mauricio Reyes Torres IK,
Zimmermann K.
Permutation parity machines for neural synchronization..
Journal of Physics A: Mathematical and Theoretical..
2009 Apr.;
42.((19),):
[DOI]
Paul Lokuciejewski HF,
Marwedel P.
A Fast and Precise Static Loop Analysis based on Abstract Interpretation, Program Slicing and Polytope Models.. In:
In Proceedings of the International Symposium on Code Generation and Optimization (CGO).
Seattle / USA:
2009 Mar..
p. 136-146.
[DOI]
Wille R,
Fey G,
Große D,
Eggersglüß S,
Drechsler R.
SWORD: A SAT like prover using word level information.. In:
VLSI-SoC: Advanced Topics on Systems on a Chip.
Springer;
2009.
p. 175-192.
TODO
Drechsler R,
Eggersglüß S,
Fey G,
Tille D.
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern..
it - Information Technology..
2009;
102-111.
Drechsler R,
Eggersglüß S,
Fey G,
Tille D.
Test Pattern Generation using Boolean Proof Engines..
Springer;
2009.
Drechsler R,
Eggersglüß S,
Fey G,
Tille D.
SAT-based Automatic Test Pattern Generation.. In:
Evolutionary Test Generation Dagstuhl-Seminar.
2009.
Frehse S,
Fey G,
Sülflow A,
Drechsler R.
Robustness Check for Multiple Faults using Formal Techniques.. In:
EUROMICRO Symposium on Digital System Design (DSD).
2009.
p. 85-90.
Frehse S,
Fey G,
Sülflow A,
Drechsler R.
Robustness Check for Multiple Faults using Formal Techniques.. In:
Workshop on Constraints in Formal Verification (CFV).
2009.
Nakura T,
Tatemura Y,
Fey G,
Ikeda M,
Komatsu S,
Asada K.
SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults.. In:
European Conference on Circuit Theory and Design (ECCTD).
2009.
p. 643-647.
2008
Sülflow A,
Fey G,
Bloem R,
Drechsler R.
Using Unsatisfiable Cores to Debug Multiple Design Errors.. In:
Great Lakes Symp. VLSI (GLS).
2008.
p. 77-82.
Sülflow A,
Fey G,
Bloem R,
Drechsler R.
Debugging Design Errors by Using Unsatisfiable Cores.. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
2008.
p. 159-168.
Sülflow A,
Fey G,
Drechsler R.
Experimental Studies on SMT-based Debugging.. In:
IEEE Workshop on RTL and High Level Testing (WRTLT).
2008.
p. 93-98.
Sülflow A,
Fey G,
Frehse S,
Kühne U,
Drechsler R.
Computing Bounds for Fault Tolerance using Formal Techniques.. In:
Workshop on Design for Reliability and Variability (DRV).
2008.
Rogin F,
Klotz T,
Fey G,
Drechsler R,
Rülke S.
Automatic Generation of Complex Properties for Hardware Designs.. In:
Design, Automation and Test in Europe (DATE).
2008.
p. 545-548.
Rogin F,
Klotz T,
Rülke S,
Fey G,
Drechsler R.
Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs.. In:
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS).
2008.
Fey G,
Sülflow A,
Frehse S,
Kühne U,
Drechsler R.
Formaler Nachweis der Fehlertoleranz von Schaltkreisen.. In:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE).
2008.
p. 75-82.
Fey G,
Bernasconi A,
Ciriani V,
Drechsler R.
On the Construction of Small Fully Testable Circuits with Low Depth..
Microprocessors and Microsystems (MICPRO)..
2008;
263-269.
Fey G,
Drechsler R.
Synthesis for Detection of Transient Faults.. In:
IEICE Workshop on Dependable Computing.
2008.
p. 161-166.
Fey G,
Drechsler R.
A Basis for Formal Robustness Checking.. In:
Int'l Symposium on Quality Electronic Design (ISQED).
2008.
p. 784-789.
Fey G,
Drechsler R.
Robustness and Usability in Modern Design Flows..
Springer;
2008.
Fey G,
Komatsu S,
Furukawa Y,
Fujita M.
Targeting Leakage Constraints during ATPG.. In:
Asian Test Symposium (ATS).
2008.
p. 225-230.
Fey G,
Komatsu S,
Furukawa Y,
Fujita M.
Targeting Leakage Constraints during ATPG.. In:
IEEE Int'l Workshop on Silicon Debug and Diagnosis (SDD).
2008.
Fey G,
Staber S,
Bloem R,
Drechsler R.
Automatic Fault Localization for Property Checking..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2008;
1138-1149.
Fey G,
Staber S,
Bloem R,
Drechsler R.
Automatic Fault Localization for Property Checking..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2008;
1138-1149.
TODO
(Ed.) HF.
Proceedings of the 11th International Workshop on Software & Compilers for Embedded Systems (SCOPES)..
Munich / Germany:
ACM;
2008 Mar..
[File]
Paul Lokuciejewski HF,
Marwedel P.
WCET-driven Cache-based Procedure Positioning Optimizations.. In:
In Proceedings of the 20th Euromicro Conference on Real-Time Systems (ECRTS).
Prague / Czech Republic:
2008 Jul..
p. 321-330.
[DOI]
Paul Lokuciejewski PM,
Theiling H.
WCET-Driven, Code-Size Critical Procedure Cloning.. In:
In Proceedings of the 11th International Workshop on Software & Compilers for Embedded Systems (SCOPES).
Munich / Germany:
2008 Mar..
p. 21-30.
TODO
TODO
Wille R,
Fey G,
Messing M,
Angst G,
Linhard L,
Drechsler R.
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.. In:
EUROMICRO Symposium on Digital System Design (DSD).
2008.
p. 542-549.
Drechsler R,
Eggersglüß S,
Fey G,
Glowatz A,
Hapke F,
Schloeffel J,
Tille D.
On Acceleration of SAT-based ATPG for Industrial Designs..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2008;
1329-1333.
Zoya Ignatova IMM,
Zimmermann K.
DNA Computing Models..
Springer;
2008 Jul..
[DOI]