2018

  • Claire Pagetti, Julien Forget, Heiko Falk, Dominic Oehlert and Arno Luppold.
    Automated generation of time-predictable executables on multi-core hardware.
    In Proceedings of the 26th International Conference on Real-Time Networks and Systems (RTNS), Poitiers / France, October 2018.
    [Abstract]

  • Karl-Heinz Zimmermann.
    Computability Theory.
    8. Edition, Hamburg University of Technology, July 2018.
    [Abstract] [pdf] [doi: 10.15480/882.1714]

  • Kateryna Muts, Arno Luppold and Heiko Falk.
    Multi-Objective Optimization for the Compiler of Hard Real-Time Systems.
    In Proceedings of the 23rd International Symposium on Mathematical Programming (ISMP), Bordeaux / France, July 2018.
    [Abstract]

  • Dominic Oehlert, Arno Luppold and Heiko Falk.
    Compilation for Real-Time Systems - An Overview of the WCET-Aware C Compiler WCC.
    In Proceedings of the 9th International Workshop on Analysis Tools and Methodologies for Embedded and Real-Time Systems (WATERS), Barcelona / Spain, July 2018.
    [Abstract]

  • Dominic Oehlert, Selma Saidi and Heiko Falk.
    Compiler-Based Extraction of Event Arrival Functions for Real-Time Systems Analysis.
    In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS), pages 4:1-4:22, Barcelona / Spain, July 2018.
    [Abstract] [pdf] [doi: 10.4230/LIPIcs.ECRTS.2018.4]

  • Kateryna Muts, Arno Luppold and Heiko Falk.
    Multi-Criteria Compiler-Based Optimization of Hard Real-Time Systems.
    In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES), pages 54-57, St. Goar / Germany, May 2018.
    [Abstract] [pdf] [doi: 10.1145/3207719.3207730]

  • Dominic Oehlert, Arno Luppold and Heiko Falk.
    Mitigating Data Cache Aging through Compiler-Driven Memory Allocation.
    In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES), pages 58-61, St. Goar / Germany, May 2018.
    [Abstract] [pdf] [doi: 10.1145/3207719.3207731]

  • Mikko Roth, Arno Luppold and Heiko Falk.
    Measuring and Modeling Energy Consumption of Embedded Systems for Optimizing Compilers.
    In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES), pages 86-89, St. Goar / Germany, May 2018.
    [Abstract] [pdf] [doi: 10.1145/3207719.3207729]

  • Dominic Oehlert and Heiko Falk.
    WCET Analysis of Automotive Buses using WCC.
    In Proceedings of the DATE Workshop on New Platforms for Future Cars, Dresden / Germany, March 2018.
    [Abstract] [pdf]

  • Karl Janson and Carl Johann Treudler and Thomas Hollstein and Jaan Raik and Maksim Jenihhin and Goerschwin Fey.
    Software-Level TMR Approach for On-Board Data Processing in Space Applications.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2018.


  • Gianluca Martino and Heinz Riener and Goerschwin Fey.
    Coverage-Guided CTL Property Enumeration for Design Understanding of Sequential Systems.
    Int'l Workshop on Logic Synthesis (IWLS), 2018.


  • Jan Malburg and Heinz Riener and Goerschwin Fey.
    Mining Latency Guarantees for RTL Designs.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), 2018.


  • Abraham Temesgen Tibebu and Goerschwin Fey.
    Augmenting All Solutions SAT Solving for Circuits with Structural Information.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2018.


2017

  • Karl-Heinz Zimmermann.
    Computability Theory.
    7. Edition, Hamburg University of Technology, July 2017.
    [Abstract] [pdf] [doi: 10.15480/882.1401]

  • Heiko Falk.
    Timing Analysis and Code Optimization for Massively-Parallel Real-Time Systems.
    Invited Talk at the HiPEAC Autumn Computing Systems Week (CSW), Stuttgart / Germany, October 2017.


  • Heiko Falk.
    Compilation Techniques for Parallel, Safety-Critical Systems with Real-Time Constraints.
    Tutorial at the Embedded Systems Week (ESWEEK), Seoul / South Korea, October 2017.


  • Dominic Oehlert, Arno Luppold and Heiko Falk.
    Bus-aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems.
    In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS), pages 1:1-1:22, Dubrovnik / Croatia, June 2017.
    [Abstract] [pdf] [doi: 10.4230/LIPIcs.ECRTS.2017.1]

  • Peter Marwedel, Heiko Falk, and Olaf Neugebauer.
    Memory-Aware Optimization of Embedded Software for Multiple Objectives.
    In S. Ha and J. Teich (Eds.): Handbook of Hardware/Software Codesign, Springer, June 2017.
    [Abstract] [doi: 10.1007/978-94-017-7358-4_27-2]

  • Arno Luppold and Heiko Falk.
    Schedulability-Aware SPM Allocation for Preemptive Hard Real-Time Systems with Arbitrary Activation Patterns.
    In Proceedings of Design, Automation and Test in Europe (DATE), pages 1074-1079, Lausanne / Switzerland, March 2017.
    [Abstract] [pdf] [doi: 10.23919/DATE.2017.7927149]

  • Eberle Rambo, Selma Saidi and Rolf Ernst.
    Designing Networks-on-Chip for High Assurance Real-Time Systems.
    In Proceedings of the International Symposium on Dependable computing (PRDC), Christchurch / New Zealand, January 2017.
    [Abstract]

  • Gökçe Aydos and Goerschwin Fey.
    Empirical Results on Parity-based Soft Error Detection with Software-based Retry.
    In Microprocessors and Microsystems (MICPRO), pages 62-68, 2017.
    [doi: 10.1016/j.micpro.2016.09.009]

  • Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey.
    A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.
    In Journal of Electronic Testing: Theory and Applications (JETTA), pages 53-64, 2017.
    [doi: 10.1007/s10836-016-5637-6]

  • Tino Flenker and Goerschwin Fey.
    Mapping Abstract and Concrete Hardware Models for Design Understanding.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2017.


  • Tino Flenker and Jan Malburg and Görschwin Fey and Serhiy Avramenko and Massimo Violante and Matteo Sonza Reorda.
    Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.
    IEEE Annual Symposium on VLSI (ISVLSI), 2017.


  • Jan Malburg and Tino Flenker and Goerschwin Fey.
    Property Mining using Dynamic Dependency Graphs.
    ASP Design Automation Conference (ASPDAC), pages 244-250, 2017.


  • Jan Malburg and Heinz Riener and Goerschwin Fey.
    Mining Latency Guarantees for RT-level Designs.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2017.


  • Meß, Jan-Gerd and Schmidt, Robert and Fey, Goerschwin.
    Adaptive Compression Schemes for Housekeeping Data.
    IEEE Aerospace Conference (AEROCONF), 2017.


  • Heinz Riener and Rüdiger Ehlers and Goerschwin Fey.
    CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification.
    ASP Design Automation Conference (ASPDAC), pages 251-256, 2017.


  • Heinz Riener and Ruediger Ehlers and Goerschwin Fey.
    Counterexample-Guided EF Synthesis of Boolean Functions.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017.


  • Heinz Riener and Goerschwin Fey.
    Computing Exact Fault Candidates Incrementally.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2017.


  • Heinz Riener and Robert Koenighofer and Goerschwin Fey and Roderick Bloem.
    SMT-Based CPS Parameter Synthesis.
    Applied Verification for Continuous and Hybrid Systems (ARCH), pages 126-133, 2017.


  • Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey.
    Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.
    IEEE International On-Line Testing Symposium (IOLTS), pages 240-243, 2017.
    [doi: 10.1109/IOLTS.2017.8046245]

  • Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey.
    Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.
    IEEE International On-Line Testing Symposium (IOLTS), 2017.


  • Niels Thole and Goerschwin Fey.
    Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2017.


2016

  • Jorge Echavaria, Stefan Wildermann, Andreas Becher, Jürgen Teich and Daniel Ziener.
    FAU: Fast Approximate Adder Units on LUT-Based FPGAs.
    In Proceedings of the International Conference on Field Programmable Technology (FPT), Xi'an / China, December 2016.


  • Thorbjörn Posewsky and Daniel Ziener.
    Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing.
    Best Paper Award. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun / Mexico, December 2016.
    [Abstract] [pdf]

  • Karl-Heinz Zimmermann.
    Computability Theory.
    6. Edition, Hamburg University of Technology, July 2016.
    [Abstract] [pdf] [doi: 10.15480/882.1309]

  • Heiko Falk.
    Achieving Timing Predictability by Combining Models.
    Invited Talk at the Dagstuhl Seminar 16441 on Adaptive Isolation for Predictability and Security, Schloss Dagstuhl / Germany, November 2016.


  • Adam Kostrzewa, Sebastian Tobuschat, Selma Saidi and Rolf Ernst.
    Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chips.
    In Proceedings of the 24th International Conference on Real-Time Networks and Systems (RTNS), pages 215-224, Brest / France, October 2016.
    [Abstract] [doi: 10.1145/2997465.2997466]

  • Adam Kostrzewa, Selma Saidi and Rolf Ernst.
    Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network.
    In Proceedings of the 14th ACM/IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), pages 37-46, Pittsburgh / USA, October 2016.
    [Abstract]

  • Adam Kostrzewa, Sebastian Tobuschat, Selma Saidi and Rolf Ernst.
    Safe and Dynamic Traffic Rate Control for Networks-on-Chips.
    In Proceedings of the 10th International Symposium on Networks-on-Chip (NOCS), pages 1-8, Nara / Japan, August 2016.
    [Abstract]

  • Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt and Helmut Weber.
    FPGA-Based Dynamically Reconfigurable SQL Query Processing.
    In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 9, No. 4, pages 25:1-25:24, ACM, August 2016.
    [Abstract] [doi: 10.1145/2845087]

  • Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann and Simon Wegener.
    TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research.
    In Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis (WCET), pages 2:1-2:10, Toulouse / France, July 2016.
    [Abstract] [pdf] [doi: 10.4230/OASIcs.WCET.2016.2]

  • Wolfgang Büter, Dominic Oehlert and Alberto García-Ortiz.
    ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition.
    In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pages 1-6, Tallinn / Estonia, June 2016.
    [Abstract] [doi: 10.1109/ReCoSoC.2016.7533909]

  • Heiko Falk.
    WCET-Aware Compilation and Optimization for Real-Time Systems.
    Invited Talk at the VERIMAG Laboratory, University Grenoble Alpes, Grenoble / France, June 2016.


  • Dirk Koch, Daniel Ziener and Frank Hannig.
    FPGA versus Software Programming: Why, When, and How?.
    In Dirk Koch, Frank Hannig and Daniel Ziener (Eds.): FPGAs for Software Programmers, chapter 1, pages 1-21, Springer, June 2016.
    [Abstract] [doi: 10.1007/978-3-319-26408-0_1]

  • Dirk Koch, Frank Hannig and Daniel Ziener.
    FPGAs for Software Programmers.
    Springer, June 2016.
    [Abstract] [doi: 10.1007/978-3-319-26408-0]

  • Andreas Becher, Jorge Echavaria, Daniel Ziener, Stefan Wildermann and Jürgen Teich.
    A LUT-Based Approximate Adder.
    In Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC / USA, May 2016.
    [Abstract] [doi: 10.1109/FCCM.2016.16]

  • Dominic Oehlert, Arno Luppold and Heiko Falk.
    Practical Challenges of ILP-based SPM Allocation Optimizations.
    In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES), pages 86-89, St. Goar / Germany, May 2016.
    [Abstract] [pdf] [doi: 10.1145/2906363.2906371]

  • Arno Luppold, Christina Kittsteiner and Heiko Falk.
    Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems.
    In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES), pages 77-85, St. Goar / Germany, May 2016.
    [Abstract] [pdf] [doi: 10.1145/2906363.2906369]

  • Heiko Falk and Arno Luppold.
    Schedulability-Aware Code Optimization for Multi-Task Real-Time Systems.
    Invited Talk at the Workshop on Analysis vs. Synthesis in Embedded Systems Design, Paris / France, March 2016.


  • Adam Kostrzewa, Selma Saidi, Leonardo Ecco and Rolf Ernst.
    Dynamic admission control for real-time networks-on-chips.
    In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pages 719-724, Macao, January 2016.
    [Abstract]

  • Adam Kostrzewa, Selma Saidi and Rolf Ernst.
    Slack-based resource arbitration for real-time Networks-on-Chip.
    In Proceedings of Design, Automation and Test in Europe (DATE), pages 1012-1017, Dresden / Germany, January 2016.
    [Abstract]

  • Eberle Rambo, Selma Saidi and Rolf Ernst.
    Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip.
    In Proceedings of Design, Automation and Test in Europe (DATE), pages 103-108, Dresden / Germany, January 2016.
    [Abstract]

  • Gadi Aleksandrowicz and Eli Arbel and Roderick Bloem and Timon ter Braak and Sergei Devadze and Goerschwin Fey and Maksim Jenihhin and Artur Jutman and Hans G. Kerkhoff and Robert Könighofer and Jan Malburg and Shiri Moran and Jaan Raik and Gerard Rauwerda and Heinz Riener and Franz Röck and Konstantin Shibin and Kim Sunesen and Jinbo Wan and Yong Zhao.
    Designing Reliable Cyber-Physical Systems.
    Forum on Specification and Design Languages (FDL), 2016.


  • Gökçe Aydos and Goerschwin Fey.
    Exploiting Error Detection Latency for Parity-based Soft Error Detection.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2016.
    [doi: 10.1109/DDECS.2016.7482440]

  • Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey and Jan-Gerd Meß and Robert Schmidt.
    On the robustness of compression algorithms for space applications.
    IEEE International On-Line Testing Symposium (IOLTS), 2016.


  • Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey.
    Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables.
    IEEE Latin-American Test Symposium (LATS), pages 14-19, 2016.
    [doi: 10.1109/LATW.2016.7483332]

  • Tino Flenker and Goerschwin Fey.
    Matching Abstract and Concrete Hardware Models for Design Understanding.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2016.


  • Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken.
    Multilevel Design Understanding: From Specification to Logic.
    IEEE/ACM Int'l Conf. on CAD (ICCAD), 2016.


  • Goerschwin Fey and Jaan Raik (Organizers).
    Designing Reliable Cyber-Physical Systems.
    Forum on Specification and Design Languages (FDL), 2016.


  • Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken.
    Multilevel Design Understanding: From Specification to Logic (Special Session).
    IEEE/ACM Int'l Conf. on CAD (ICCAD), 2016.


  • Niklas Krafczyk and Heinz Riener and Goerschwin Fey.
    WCET Overapproximation for Software in the Context of a Cyber-Physical System.
    IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC), 2016.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Debugging hardware designs using dynamic dependency graphs.
    In Microprocessors and Microsystems (MICPRO), pages 347-359, 2016.


  • Jan Malburg and Tino Flenker and Goerschwin Fey.
    Generating Good Properties from a Small Number of Use Cases.
    International Verification and Security Workshop (IVSW), 2016.


  • Jan-Gerd Meß and Robert Schmidt and Goerschwin Fey and Frank Dannemann.
    On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms.
    ESA International Tracking, Telemetry and Command Systems for Space Applications (TTC), 2016.


  • Heinz Riener and Goerschwin Fey.
    Exact Diagnosis using Boolean Satisfiability.
    IEEE/ACM Int'l Conf. on CAD (ICCAD), pages 53:1-53:8, 2016.
    [doi: 10.1145/2966986.2967036]

  • Heinz Riener and Goerschwin Fey.
    Counterexample-Guided Diagnosis.
    International Verification and Security Workshop (IVSW), 2016.


  • Heinz Riener and Finn Haedicke and Stefan Frehse and Mathias Soeken and Daniel Große and Rolf Drechsler and Goerschwin Fey.
    metaSMT: Focus On Your Application And Not On Solver Integration.
    In International Journal on Software Tools for Technology Transfer (STTT), pages 1-17, 2016.
    [doi: 10.1007/s10009-016-0426-1]

  • Niels Thole and Lorena Anghel and Goerschwin Fey.
    A Hybrid Algorithm to Conservatively Check the Robustness of Circuits (extended abstract).
    IEEE European Test Symposium (ETS), pages 2, 2016.
    [doi: 10.1109/ETS.2016.7519326]

  • Niels Thole and Lorena Anghel and Goerschwin Fey.
    A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.
    IEEE Annual Symposium on VLSI (ISVLSI), pages 278-283, 2016.
    [doi: 10.1109/ISVLSI.2016.106]

  • Niels Thole and Lorena Anghel and Goerschwin Fey.
    A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2016.


  • Niels Thole and Heinz Riener and Goerschwin Fey.
    Equivalence Checking on ESL Utilizing A Priori Knowledge.
    Forum on Specification and Design Languages (FDL), 2016.


  • Sallam Abualhaija, Karl-Heinz Zimmermann.
    D-Bees: A novel method inspired by bee colony optimization for solving word sense disambiguation.
    In Swarm and Evolutionary Computation, Vol. 27, pages 188-195, 2016.


  • Karl-Heinz Zimmermann.
    Algebraic Statistics.
    3. Edition, Hamburg University of Technology, January 2016.
    [pdf]

2015

  • Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener and Jürgen Teich.
    A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering.
    In Proceedings of the International Conference on Field-Programmable Technology (FPT), Queenstown / New Zealand, December 2015.
    [Abstract] [doi: 10.1109/FPT.2015.7393148]

  • Andreas Becher, Jorge Echavarria, Daniel Ziener and Jürgen Teich.
    Approximate Adder Structures on FPGAs.
    In Proceedings of the Workshop on Approximate Computing (AC), Paderborn / Germany, October 2015.
    [Abstract]

  • Karl-Heinz Zimmermann.
    Computability Theory.
    5. Edition, Hamburg University of Technology, July 2015.
    [Abstract] [pdf] [doi: 10.15480/882.1247]

  • Arno Luppold and Heiko Falk.
    Schedulability aware WCET-Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems.
    In Proceedings of the 18th International Workshop on Software & Compilers for Embedded Systems (SCOPES), pages 101-104, St. Goar / Germany, June 2015.
    [Abstract] [pdf] [doi: 10.1145/2764967.2771930]

  • Arno Luppold and Heiko Falk.
    Code Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems.
    In Proceedings of the 18th International Symposium on Real-Time Distributed Computing (ISORC), pages 35-42, Auckland / New Zealand, April 2015.
    [Abstract] [pdf] [doi: 10.1109/ISORC.2015.8]

  • Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo and Heiko Falk.
    Real-Time Task Scheduling on Island-Based Multi-Core Platforms.
    In IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 26, No. 2, pages 538-550, IEEE, February 2015.
    [Abstract] [doi: 10.1109/TPDS.2013.2297308]

  • Gökçe Aydos and Goerschwin Fey.
    Empirical Results on Parity-based Soft Error Detection with Software-based Retry.
    IEEE Nordic Circuits and Systems Conference (NORCAS), 2015.


  • Mehdi Dehbashi and Goerschwin Fey.
    Debug Automation from Pre-Silicon to Post-Silicon.
    pages 171, 2015.


  • Mehdi Dehbashi and Goerschwin Fey.
    Transaction-based online debug for NoC-based multiprocessor SoCs.
    In Microprocessors and Microsystems (MICPRO), pages 157-166, 2015.
    [doi: http://dx.doi.org/10.1016/j.micpro.2015.03.003]

  • Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers).
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
    2015.


  • Tino Flenker and André Sülflow and Goerschwin Fey.
    Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation.
    Asian Test Symposium (ATS), pages 145-150, 2015.


  • Jabier Martinez and Jan Malburg and Tewfik Ziadi and Goerschwin Fey.
    Towards analysing feature locations through testing traces with BUT4Reuse.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), pages 10-15, 2015.


  • Heinz Riener and Rüdiger Ehlers and Goerschwin Fey.
    Path-Based Program Repair.
    International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS, pages 22-32, 2015.


  • Heinz Riener and Michael Kirkedal Thomsen and Goerschwin Fey.
    Execution Tracing of C Code for Formal Analysis (Extended Abstract).
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 160-164, 2015.


  • Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz.
    Conservatively Analyzing Transient Faults.
    IEEE Annual Symposium on VLSI (ISVLSI), pages 50-55, 2015.


  • Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz.
    Analyzing an SET at Gate Level using a Conservative Approach.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2015.


  • Niels Thole and Heinz Riener and Fey, Goerschwin.
    Equivalence Checking on System Level using A Priori Knowledge.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 177-182, 2015.


  • Trond Ytterdal and Snorre Aunet and General Chairs and Bjørn B. Larsen and Görschwin Fey (editors).
    22nd European conference on circuit theory and design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015.
    European Conference on Circuit Theory and Design (ECCTD), 2015.


  • Natalia Schmidt.
    Gröbner Bases in Coding Theory.
    pages 180, Dr. Huth Verlag, 2015.


  • Natalia Schmidt, Karl-Heinz Zimmermann.
    Graver bases and universal Gröbner bases for linear codes.
    In IJPAM, Vol. 98, No. 4, pages 419-441, 2015.


2014

  • Nicolas Roeser, Arno Luppold and Heiko Falk.
    Multi-Criteria Optimization of Hard Real-Time Systems.
    In Proceedings of the 8th Junior Researcher Workshop on Real-Time Computing (JRWRTC), pages 49-52, Versailles / France, October 2014.
    [Abstract] [pdf]

  • Arno Luppold and Heiko Falk.
    Schedulability-Oriented WCET-Optimization of Hard Real-Time Multitasking Systems.
    In Proceedings of the 8th Junior Researcher Workshop on Real-Time Computing (JRWRTC), pages 9-12, Versailles / France, October 2014.
    [Abstract] [pdf]

  • Sudipta Chattopadhyay, Lee Kee Chong, Abhik Roychoudhury, Timon Kelter, Peter Marwedel and Heiko Falk.
    A Unified WCET Analysis Framework for Multicore Platforms.
    © ACM, 2014. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published In ACM Transactions on Embedded Computing Systems (TECS), Vol. 13, No. 4s, ACM, July 2014.
    [Abstract] [pdf] [doi: 10.1145/2584654]

  • Muhammad Kashif Hanif.
    Mapping Dynamic Programming Algorithms on Graphics Processing Units.
    Ph.D. Thesis. Hamburg University of Technology, School of Electrical Engineering, Computer Science and Mathematics, Hamburg / Germany, July 2014.
    [Abstract] [pdf] [doi: 10.15480/882.1184]

  • Natalia Dück and Karl-Heinz Zimmermann.
    Heuristic decoding of linear codes using commutative algebra.
    In Designs, Codes and Cryptography (DCC), Vol. 76, No. 1, pages 23-35, Springer, July 2014.
    [Abstract] [doi: 10.1007/s10623-014-0008-8]

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