Publications on WCET-Aware Compilation

[180981]
Title: WCET Analysis of Shared Caches in Multi-Core Architectures using Event-Arrival Curves. <em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>
Written by: Thilo Fischer and Heiko Falk
in: April (2023).
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how published: 23-95 FF23 DATE
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Note: tfischer, hfalk, ESD, WCC

Abstract: We propose a novel analysis approach for shared LRU caches to classify accesses as definitive cache hits or potential misses. In this approach inter-core cache interference is modelled as an event stream. Thus, by analyzing the timing between subsequent accesses to a particular cache block, it is possible to bound the inter-core interference. This perspective allows us to classify accesses as cache hits or potential misses using a data-flow analysis. We compare the performance of the presented approach to a partitioning of the shared cache.