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Timing Analysis on Code-Level (TACLe)
Fact Sheet
| Acronym | TACLe |
|---|---|
| Name | Timing Analysis on Code-Level |
| Homepage | www.tacle.eu |
| Role of TUHH | Action Vice Chair, member of Working Groups 1, 2 and 4 |
| Start Date | 07/11/2012 |
| End Date | 06/11/2016 |
| Funds Donor | COST Office Brussels |
Summary
TACLe is a four years lasting COST Action funded by the COST Office in Brussels.
Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.
This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.
TACLe Publications of the Embedded Systems Design Group
| [176915] |
| Title: Partitioned Scheduling for Real-Time Tasks on Multiprocessor Embedded Systems with Programmable Shared SRAMs. <em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em> |
| Written by: Che-Wei Chang, Jian-Jia Chen, Waqaas Munawar, Tei-Wei Kuo and Heiko Falk |
| in: October (2012). |
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| on pages: 153-162 |
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| Series: 20121008-emsoft-chang.pdf |
| Address: Tampere / Finland |
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| ISBN: 10.1145/2380356.2380384 |
| how published: 12-25 CCM+12 EMSOFT |
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Note: hfalk, ESD, emp2, tacle
Abstract: This work is motivated by the advance of multiprocessor system architecture, in which the allocation of tasks over heterogeneous memory modules has a significant impact on the task execution. By considering two different types of memory modules with different access latencies, this paper explores joint considerations of memory allocation and real-time task scheduling to minimize the maximum utilization of processors of the system. For implicit-deadline sporadic tasks, a two-phase algorithm is developed, where the first phase determines memory allocation to derive a lower bound of the maximum utilization, and the second phase adopts worst-fit partitioning to assign tasks. It is shown that the proposed algorithm leads to a tight (2 - 2/(M+1))-approximation bound where M is the number of processors. The proposed algorithm is then evaluated with 82 realistic benchmarks from MRTC, MediaBench, UTDSP, NetBench and DSPstone, and extensive simulations are further conducted to analyze the proposed algorithm.