Timing Analysis on Code-Level (TACLe)

Fact Sheet

NameTiming Analysis on Code-Level
Role of TUHHAction Vice Chair, member of Working Groups 1, 2 and 4
Start Date07/11/2012
End Date06/11/2016
Funds DonorCOST Office Brussels


TACLe is a four years lasting COST Action funded by the COST Office in Brussels.

Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.

This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.

TACLe Publications of the Embedded Systems Design Group

Title: Code-Level Timing Analysis of Embedded Software. <em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em>
Written by: Heiko Falk, Kevin Hammond, Kim G. Larsen, Bj&ouml;rn Lisper and Stefan M. Petters
in: October (2012).
Volume: Number:
on pages: 163-164
Series: 20121009-emsoft-falk.pdf
Address: Tampere / Finland
ISBN: 10.1145/2380356.2380386
how published: 12-20 FHL+12 EMSOFT

Note: hfalk, ESD, tacle

Abstract: Embedded systems are often business- or safety-critical, with strict timing requirements that have to be met for the information-processing. Code-level timing analysis (used to analyse software running on some given hardware w. r. t. its timing properties) is an indispensable technique for ascertaining whether or not these requirements are met. However, recent developments in hardware, especially multi-core processors, and in software organisation render analysis increasingly more difficult, thus challenging the evolution of timing analysis techniques. This special session aims to give an overview over the current state of the art and the future challenges w. r. t. code-level timing analysis and introduces TACLe, a recently started EU-funded networking activity targeting these challenges.