Timing Analysis on Code-Level (TACLe)

Fact Sheet

NameTiming Analysis on Code-Level
Role of TUHHAction Vice Chair, member of Working Groups 1, 2 and 4
Start Date07/11/2012
End Date06/11/2016
Funds DonorCOST Office Brussels


TACLe is a four years lasting COST Action funded by the COST Office in Brussels.

Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.

This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.

TACLe Publications of the Embedded Systems Design Group

Title: Schedulability aware WCET-Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems. <em>In Proceedings of the 18th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>
Written by: Arno Luppold and Heiko Falk
in: June (2015).
Volume: Number:
on pages: 101-104
Series: 20150601-scopes-luppold.pdf
Address: St. Goar / Germany
ISBN: 10.1145/2764967.2771930
how published: 15-70 LuFa15b SCOPES

Note: aluppold, hfalk, ESD, emp2, tacle, WCC

Abstract: In hard real-time multitasking systems, applying WCET-oriented code optimizations to individual tasks may not lead to optimal results with regard to the system's schedulability. We propose an approach based on Integer-Linear Programming which is able to perform schedulability aware code optimizations for periodic task sets with fixed priorities. We evaluate our approach by using a static instruction SPM optimization for the Infineon TriCore microcontroller.