Timing Analysis on Code-Level (TACLe)

Fact Sheet

NameTiming Analysis on Code-Level
Role of TUHHAction Vice Chair, member of Working Groups 1, 2 and 4
Start Date07/11/2012
End Date06/11/2016
Funds DonorCOST Office Brussels


TACLe is a four years lasting COST Action funded by the COST Office in Brussels.

Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.

This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.

TACLe Publications of the Embedded Systems Design Group

Title: Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems. <em>In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>
Written by: Arno Luppold, Christina Kittsteiner and Heiko Falk
in: May (2016).
Volume: Number:
on pages: 77-85
Series: 20160524-scopes-luppold.pdf
Address: St. Goar / Germany
ISBN: 10.1145/2906363.2906369
how published: 16-75 LKF16 SCOPES

Note: aluppold, hfalk, ESD, emp2, tacle, WCC

Abstract: To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. <br /> We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.