Timing Analysis on Code-Level (TACLe)

Fact Sheet

NameTiming Analysis on Code-Level
Role of TUHHAction Vice Chair, member of Working Groups 1, 2 and 4
Start Date07/11/2012
End Date06/11/2016
Funds DonorCOST Office Brussels


TACLe is a four years lasting COST Action funded by the COST Office in Brussels.

Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.

This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.

TACLe Publications of the Embedded Systems Design Group

Title: Practical Challenges of ILP-based SPM Allocation Optimizations. <em>In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>
Written by: Dominic Oehlert, Arno Luppold and Heiko Falk
in: May (2016).
Volume: Number:
on pages: 86-89
Series: 20160524-scopes-oehlert.pdf
Address: St. Goar / Germany
ISBN: 10.1145/2906363.2906371
how published: 16-70 OLK16 SCOPES

Note: doehlert, aluppold, hfalk, ESD, emp2, tacle, WCC

Abstract: Scratchpad Memory (SPM) allocation is a well-known technique for compiler-based code optimizations. Integer-Linear Programming has been proven to be a powerful technique to determine which parts of a program should be moved to the SPM. Although the idea is quite straight-forward in theory, the technique features several challenges when being applied to modern embedded systems. In this paper, we aim to bring out the main issues and possible solutions which arise when trying to apply those optimizations to existing hardware platforms.