Generation and Optimization of Real-Time Code for Embedded Multiprocess and Multiprocessor Systems (E = Mp2)
|Acronym||E = Mp2|
|Name||Generation and Optimization of Real-Time Code for Embedded Multiprocess and Multiprocessor Systems|
(in German: Generierung und Optimierung von Echtzeitfähigem Code für Eingebettete Multiprozess- und Multiprozessor-Systeme)
|Role of TUHH||Applicant|
|Funds Donor||Deutsche Forschungsgemeinschaft (DFG)|
During the design of safety-critical real-time systems like, e.g., airbag or flight attitude controllers, their behavior is specified at a high abstraction level. Compilers are an indispensible tool on the way from such a model-based specification to an actual implementation. For singlecore and singleprocess systems, compilers have recently been extended to support real-time properties already during compilation. For multiprocess and multiprocessor systems, compilers currently lack such a support despite of the increasing relevance of such parallel systems.
E = Mp2 aims to provide a software development environment for multiprocess and multiprocessor systems which produces efficient and optimized program code that provably meets real-time constraints. For this purpose, it has to be clarified how compiler and scheduler of an operating system need to cooperate. In addition, novel timing models supporting response times of processes and schedulability of entire systems need to be developed. Based on these timing models, novel compiler optimizations targeting on worst-case timing aspects and schedulability are designed.
In multiprocess systems, tasks can preempt each other and thus interfere. E = Mp2 develops compiler optimizations considering such context switches and scheduling strategies. In multiprocessor systems, different cores can access shared resources (e.g., buses or memories) at the same time and thus can cause additional interference. Therefore, this project works on compiler optimizations minimizing the worst-case timing of such systems by considering accesses to shared resources.
E = Mp2 Publications of the Embedded Systems Design Group
|Title: WCET-aware Static Locking of Instruction Caches. <em>In Proceedings of the International Symposium on Code Generation and Optimization (CGO)</em>|
|Written by: Sascha Plazar, Heiko Falk, Jan C. Kleinsorge and Peter Marwedel|
|in: April (2012).|
|on pages: 44-52|
|Address: San Jose / USA|
|how published: 12-70 PKFM12 CGO|
Note: hfalk, ESD, emp2, WCC
Abstract: In the past decades, embedded system designers moved from simple, predictable system designs towards complex systems equipped with caches. This step was necessary in order to bridge the increasingly growing gap between processor and memory system performance. Static analysis techniques had to be developed to allow the estimation of the cache behavior and an upper bound of the execution time of a program. This bound is called worst-case execution time (WCET). Its knowledge is crucial to verify whether hard real-time systems satisfy their timing constraints, and the WCET is a key parameter for the design of embedded systems.<br /> In this paper, we propose a WCET-aware optimization technique for static I-cache locking which improves a program's performance and predictability. To select the memory blocks to lock into the cache and avoid time consuming repetitive WCET analyses, we developed a new algorithm employing integer-linear programming (ILP). The ILP models the worst-case execution path (WCEP) of a program and takes the influence of locked cache contents into account. By modeling the effect of locked memory blocks on the runtime of basic blocks, the overall WCET of a program can be minimized. We show that our optimization is able to reduce the estimated WCET (abbr. WCETest) of real-life benchmarks by up to 40.8%. At the same time, our proposed approach is able to outperform a regular cache by up to 23.8% in terms of WCETest.