Generation and Optimization of Real-Time Code for Embedded Multiprocess and Multiprocessor Systems (E = Mp2)

Fact Sheet

AcronymE = Mp2
NameGeneration and Optimization of Real-Time Code for Embedded Multiprocess and Multiprocessor Systems
(in German: Generierung und Optimierung von Echtzeitfähigem Code für Eingebettete Multiprozess- und Multiprozessor-Systeme)
Role of TUHHApplicant
Start Date01/02/2012
End Date30/09/2017
Funds DonorDeutsche Forschungsgemeinschaft (DFG)


During the design of safety-critical real-time systems like, e.g., airbag or flight attitude controllers, their behavior is specified at a high abstraction level. Compilers are an indispensible tool on the way from such a model-based specification to an actual implementation. For singlecore and singleprocess systems, compilers have recently been extended to support real-time properties already during compilation. For multiprocess and multiprocessor systems, compilers currently lack such a support despite of the increasing relevance of such parallel systems.

E = Mp2 aims to provide a software development environment for multiprocess and multiprocessor systems which produces efficient and optimized program code that provably meets real-time constraints. For this purpose, it has to be clarified how compiler and scheduler of an operating system need to cooperate. In addition, novel timing models supporting response times of processes and schedulability of entire systems need to be developed. Based on these timing models, novel compiler optimizations targeting on worst-case timing aspects and schedulability are designed.

In multiprocess systems, tasks can preempt each other and thus interfere. E = Mp2 develops compiler optimizations considering such context switches and scheduling strategies. In multiprocessor systems, different cores can access shared resources (e.g., buses or memories) at the same time and thus can cause additional interference. Therefore, this project works on compiler optimizations minimizing the worst-case timing of such systems by considering accesses to shared resources.

E = Mp2 Publications of the Embedded Systems Design Group

Title: A Unified WCET Analysis Framework for Multi-core Platforms. <em>In Proceedings of the 18th Real-Time and Embedded Technology and Applications Symposium (RTAS)</em>
Written by: Sudipta Chattopadhyay, Lee Kee Chong, Abhik Roychoudhury, Timon Kelter, Heiko Falk and Peter Marwedel
in: April (2012).
Volume: Number:
on pages: 99-108
Series: 20120418-rtas-chattopadhyay.pdf
Address: Beijing / China
ISBN: 10.1109/RTAS.2012.26
how published: 12-65 CCR+12 RTAS

Note: hfalk, ESD, emp2, WCC

Abstract: With the advent of multi-core architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this paper, we propose a unified WCET analysis framework for multi-core processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multi-core architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.