Generation and Optimization of Real-Time Code for Embedded Multiprocess and Multiprocessor Systems (E = Mp2)

Fact Sheet

AcronymE = Mp2
NameGeneration and Optimization of Real-Time Code for Embedded Multiprocess and Multiprocessor Systems
(in German: Generierung und Optimierung von Echtzeitfähigem Code für Eingebettete Multiprozess- und Multiprozessor-Systeme)
Role of TUHHApplicant
Start Date01/02/2012
End Date30/09/2017
Funds DonorDeutsche Forschungsgemeinschaft (DFG)


During the design of safety-critical real-time systems like, e.g., airbag or flight attitude controllers, their behavior is specified at a high abstraction level. Compilers are an indispensible tool on the way from such a model-based specification to an actual implementation. For singlecore and singleprocess systems, compilers have recently been extended to support real-time properties already during compilation. For multiprocess and multiprocessor systems, compilers currently lack such a support despite of the increasing relevance of such parallel systems.

E = Mp2 aims to provide a software development environment for multiprocess and multiprocessor systems which produces efficient and optimized program code that provably meets real-time constraints. For this purpose, it has to be clarified how compiler and scheduler of an operating system need to cooperate. In addition, novel timing models supporting response times of processes and schedulability of entire systems need to be developed. Based on these timing models, novel compiler optimizations targeting on worst-case timing aspects and schedulability are designed.

In multiprocess systems, tasks can preempt each other and thus interfere. E = Mp2 develops compiler optimizations considering such context switches and scheduling strategies. In multiprocessor systems, different cores can access shared resources (e.g., buses or memories) at the same time and thus can cause additional interference. Therefore, this project works on compiler optimizations minimizing the worst-case timing of such systems by considering accesses to shared resources.

E = Mp2 Publications of the Embedded Systems Design Group

Title: Bus-aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems. <em>In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS)</em>
Written by: Dominic Oehlert, Arno Luppold and Heiko Falk
in: June (2017).
Volume: Number:
on pages: 1:1-1:22
Series: 20170628-ecrts-oehlert.pdf
Address: Dubrovnik / Croatia
ISBN: 10.4230/LIPIcs.ECRTS.2017.1
how published: 17-80 OLF17 ECRTS

Note: doehlert, aluppold, hfalk, ESD, emp2, WCC

Abstract: Over the past years, multicore systems emerged into the domain of hard real-time systems. These systems introduce common buses and shared memories which heavily influence the timing behavior. We show that existing WCET optimizations may lead to suboptimal results when applied to multicore setups. Additionally we provide both a genetic and a precise Integer Linear Programming (ILP) based static instruction scratchpad memory allocation optimization which are capable of exploiting multicore properties, resulting in a WCET reduction of 26% in average compared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimization's average runtime is distinctively lower in comparison to the genetic approach. Although limiting the number of tasks per core to one and partially exploiting private instruction SPMs, we cover the most crucial elements of a multicore setup: the interconnection and shared resources.