|Title: A Unified WCET Analysis Framework for Multicore Platforms.|
|Written by: Sudipta Chattopadhyay, Lee Kee Chong, Abhik Roychoudhury, Timon Kelter, Peter Marwedel and Heiko Falk|
|in: <em>ACM Transactions on Embedded Computing Systems (TECS)</em>. July (2014).|
|Volume: <strong>13</strong>. Number: (4s),|
|how published: 14-25 CCR+14 TECS|
|Type: © ACM, 2014. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published|
Note: hfalk, ESD, emp2, tacle, WCC
Abstract: With the advent of multicore architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.