Completed Theses

2024

  • 24-90 Oltmanns (2024). Extension of the WCC Compiler Testbench by Support for Multiple Target Architectures.

  • 24-95 Singh (2024). Development of a Code Selector Ruleset for Composed Types Targeting RISC-V Processors as Part of a WCET-Aware Compiler.

2023

  • 23-70 Paulson (2023). Regression Methods to Predict WCET while Performing Function Inlining on EEMBC Benchmarks Suite.

  • 23-40 Anuradha (2023). Retiming for PyRTL.

  • 23-45 Voelcker (2023). Correction of Literal Pool Placement in a WCET-Aware Compiler for the ARM7 Architecture.

  • 23-95 Venkatarajappa (2023). Design of a Tearing Safe Wear-Leveling Algorithm for RRAM-based Storage Used in Secure Embedded Systems.

  • 23-75 Edris (2023). Analysis of the RISC-V ISA Vector Extension.

  • 23-80 Raghavendra (2023). Custom On-Chip Debugger for RISCV32.

  • 23-85 Schröder (2023). Code-Selection for C Bit-Fields in a WCET-Aware Compiler for an ARM Architecture.

  • 23-90 Sreekumar (2023). Extension of the WCC Compiler to Support an Open-Source RISC-V Floating-Point and Double-Precision Instruction Set.

  • 23-50 Barmo (2023). Erweiterung des WCC-Compilers um Parametrische Schleifengrenzen in einer High-Level Zwischendarstellung.

  • 23-55 Sainath (2023). Automation of Software Weaknesses Detection Using a Formal Approach.

  • 23-60 Tsiamis (2023). Development of a Code Selector Rule Set for Arrays for the RISC-V Architecture inside a WCET Compiler.

  • 23-65 Heinicke (2023). Code Selection for C-Strings, Function Pointers and Data Types of Small Bit Width for the RISC-V Architecture.

2022

  • 22-50 Kuhlmann (2022). Design and Test of a Code Selector Ruleset for Pointer Expressions targeting RISC-V Processors as part of a WCET-aware Compiler.

  • 22-90 Irogbarachi (2022). Defining a Scalable Life Cycle Management Security Architecture for Post-Silicon Life Cycle States Ensuring Authenticity and Integrity Based on iTrustlets.

  • 22-95 Alexander (2022). Implementation of State-of-the-Art Worst-Case End-to-End Delay Analysis for NoC-based Sytems within the WCET-Aware C Compiler.

  • 22-60 Khokhar (2022). Effiziente Objekt-Rekonstruktion durch die Zurückführung von 3D-Messdaten auf bekannte parametrisierbare Objekte.

  • 22-65 Nair (2022). HHS Analysis and Notch Detection for Electronic Enabling Valve in Forklifts.

  • 22-70 Seferi (2022). Analysis of communication in NoC interconnects in terms of routing algorithms and topologies.

  • 22-75 Abdelaziz (2022). Troubleshooting and Resolving Problems in Code-Selector Ruleset of a WCET aware C Compiler for ARM Architecture to support 64-bit Integer Data Type.

  • 22-80 Hoffmann (2022). Entwurf und Evaluation einer Bit-genauen Daten- und Wertfluss-Analyse für den RISC-V IMC-Befehlssatz.

  • 22-85 Avdevicius (2022). Design of Energy Management System in the German residential sector based on an extended Sensor Set and complex Sensor Data Exchange.

  • 22-55 Haj Mousa (2022). Function Liveness Analysis in the WCC Compiler.

  • 22-60 Mecklenburg (2022). Analyse und Evaluation von Ansätzen zur Portierung eingebetteter medizinischer Software.

  • 22-65 Sühl (2022). Stack Frame Allocation inside a Compiler for the RISC-V Processor Architecture.

2021

  • 21-75 Fischer (2021). Worst-Case Execution Time Aware Approximate Computing.

  • 21-80 Abaza (2021). Worst-Case Execution Time Analysis for C++ Based Real-Time On-Board Software Systems.

  • 21-85 Markooli Harish (2021). Low Bandwith Tracing of ARM Processors.

  • 21-55 Cinar (2021). Entwurf und Evaluation eines neuronalen Netzes zur Audio-Klassifikation der Türstellung von Baumaschinen.

  • 21-60 Oltmanns (2021). Erweiterung einer Low-Level Compiler-Zwischendarstellung um die RISC-V Befehlssatz-Architektur.

  • 21-65 Venkatarajappa (2021). Multi-Objective Static Data SPM Allocation.

  • 21-95 Ali (2021). Automatic Process for the Configuration of Windfarm Data Interfaces.

  • 21-90 Rathakrishnan (2021). Investigation and Enhancement of a Distributed Time-Triggered Bus Communication.

  • 21-70 Irogbarachi (2021). Memory management specification for low-end edge devices.

2020

  • 20-85 Ansari (2020). Compilerunterstützung für parametrische Schleifengrenzen auf Assemblersprachen-Ebene während einer WCET-Analyse.

  • 20-70 Brockes (2020). Design of a Code Selector Rule Set for the ARM Architecture to Support 64-bit Data Types within a WCET-Aware C Compiler.

  • 20-95 Becker (2020). Design of an ARM-based Execution Platform for the WCET-aware C compiler WCC.

  • 20-90 Bostelmann-Arp (2020). Efficient Code Decompression at Execution Time.

  • 20-75 Li (2020). Porting of Compiler Infrastructure for the Leon3 Processor Architecture.

  • 20-80 Abaza (2020). The Effectiveness of Data-Flow Analysis for Embedded Software Reverse-Engineering.

  • 20-55 Wulfes (2020). Automatische Belichtungsregelung einer Embedded-Linux-Kamera.

  • 20-60 Fischer (2020). Code-Selection for C-Language Constructs in a WCET-Aware Compiler for an ARM Architecture.

  • 20-65 Becker (2020). Task Allocation for Multi-Core Architectures in Hard Real-Time Systems.

2019

  • 19-90 Alseikh (2019). Modellierung der DRAM-Performance: Eine Vergleichsstudie mit dem gem5 DRAM-Simulator.

  • 19-55 Romanenkov (2019). Klassifizierung der Neutronendetektor-Signale mit Hilfe von maschinellem Lernen auf FPGAs.

  • 19-60 Marschner (2019). Designing and Testing a Code Selector Ruleset for Jump-Statements and Pointer-Expressions targeting ARM Processors as part of a WCET-aware Compiler.

  • 19-95 Jährig (2019). Modeling and Performance Analysis of Shared-Memory Multi-Core Architectures.

  • 19-75 Kowalka (2019). Multi-Objective Function Specialization based on a Function Approximation Technique.

  • 19-80 Green (2019). Erweiterung, Validierung und Charakterisierung der TACLeBench Benchmark-Sammlung.

  • 19-85 Güngör (2019). Correction Algorithm of LiDAR Data for an Autonomous Formula Vehicle.

  • 19-65 Syring (2019). Exploiting Locality for Timing Analysis of Shared DRAM in MPSoCs.

  • 19-70 Dymel (2019). Evaluation of different clustering techniques for evolutionary algorithms.

2018

  • 18-85 Lukhi (2018). Brushless DC motor control using Texas Instrument's microcontroller with Matlab/Simulink.

  • 18-90 Putta (2018). Investigating the effect of parallelization on multi-core real time systems.

  • 18-30 Patil (2018). Definition of a Java Based TPM 2.0 Security Architecture Optimized For IoT Applications in Resource Constrained Environments such as Secure Elements.

  • 18-95 Becker (2018). Development of a Code Selector Rule Set for Composed Types for the ARM Architecture inside a WCET-aware Compiler.

  • 18-65 Kowalka (2018). Multiobjective Particle Swarm Optimization applied to function specialization.

  • 18-70 Schlottmann (2018). Entwurf und Test von Analyseschnittstellen für Xilinx FPGAs.

  • 18-75 Li (2018). Investigate the performance of deep neural network using CPA (Compositional performance analysis) tools.

  • 18-80 Medhi (2018). Comparison of Measurement Platforms for Instruction Level Energy Consumption for an ARM Processor.

  • 18-35 Fischer (2018). Automatic Scheduler Generation for Hard Real-Time Systems using a WCET-Aware Compiler.

  • 18-40 Zorn (2018). Scratchpad-Allokation von Daten zur Worst-Case Execution Time Minimierung für Mehrkern-Architekturen.

  • 18-45 Nayak (2018). Architectural-level security analysis of heterogeneous multicore processors for secure embedded systems.

  • 18-50 Runge (2018). Design of a Code Selector Rule Set for Type Casting for ARM Processors as a Part of a WCET-Aware Compiler.

  • 18-55 Malessa (2018). Energy Consumption of Conditional Execution in ARM Instructions.

  • 18-60 Rohlf (2018). Vergleich und Bewertung von Echtzeitbetriebssystemen auf Dual Core System.

  • 18-62 Piontek (2018). Instruktionsscheduling für harte Multi-Core Echtzeitsysteme mit gemeinsam genutztem Datenbus.

2017

  • 17-75 Plog (2017). Developing a Code Selector's Ruleset for the ARM Processor.

  • 17-80 Vogel (2017). Cache-Analyse und -Optimierung auf der Basis von Model Checking.

  • 17-60 Lehmann (2017). Konzeption eines Echtzeitbetriebssystems zur vereinfachten Portierung der Software auf einem Eingebetteten System.

  • 17-25 Gonzalez (2017). Temporal characterization of cyber-physical attacks.

  • 17-90 Duebel (2017). Analyse von Zeigervariablen zur Abschätzung einer oberen Schranke von Schleifendurchläufen in Echtzeitsystemen.

  • 17-95 Patil (2017). Effect of Compiler Optimizations on Software Countermeasures against Fault Attacks in Smart Cards. [Abstract]

  • 17-85 Jong (2017). Designing an Autonomous Robot Navigation System Using SCADE.

  • 17-65 Busch (2017). Dynamic Data Cache Locking for Worst-Case Execution Time Optimization.

  • 17-70 Bouraffa (2017). WCC Code Selection Framework for the ARM Processor Architecture.

  • 17-30 Gonzalez (2017). Portierung einer Datenscratchpadoptimierung in das ILP-Framework des WCC.

  • 17-35 Doshi (2017). Modelling the effects of different factors on instruction-level energy consumption for an ARM-based processor architecture.

  • 17-40 Nayak (2017). Design and realization of a measurement platform for instruction-level energy consumption for an ARM processor.

  • 17-45 Luebke (2017). Plattform für die Embedded-Echtzeitverarbeitung von Zeitreihen respiratorischer Signale.

  • 17-50 Meier (2017). Entwicklung und Realisierung einer Firmware für ein mobiles Anästhesiegerät.

  • 17-55 Ahlers (2017). Diskussion eines generischen Ansatzes zur Interoperabilität von OPC UA und DDS.

2016

  • 16-70 Sieverding (2016). Reduzieren von Störeinflüssen auf Bewegungssensoren mithilfe von digitalen Filtern am Beispiel einer Navigation.

  • 16-80 Schlodinski (2016). Analysis of Methods for Reducing the Fault Injection Simulation Time of Integrated Circuits with SystemC.

  • 16-90 Schlott (2016). Entwurf eines eingebetteten Systems zur Vermeidung von unbeabsichtigten Entfaltungen der Notrutschen in Passagierflugzeugen.

  • 16-50 Minartz (2016). Entwicklung transparenter Lenkradtasten mit berührungsempflindlicher Bedienung und haptischem Feedback.

  • 16-60 Huber (2016). Design and Implementation of a Model Based Software Architecture for a Medical Ventilation System.

2015

  • 15-40 Rodrigues (2015). Operating infrastructure for an FPGA and ARM system.

  • 15-90 El-Dajani (2015). PSOSS: Ein PSHDL-Simulator auf einer SHARF basierten Zielplattform.

  • 15-50 Zambou (2015). Anbindung von Passiven Lego-Mindstorm-Sensoren an das PRHS-Framework.

  • 15-60 KKoehler (2015). Evaluation und Implementierung von Algorithmen zur Bewegungserkennung auf einem eingebetteten System mit Kameramodul.

  • 15-70 CKoehler (2015). Entwurfsmethodik für Software-Architekturen im Bereich Avionic.

  • 15-80 Kittsteiner (2015). Cache-bewusste Code-Platzierung für Scratchpad-Speicher zur Reduktion der maximalen Programmlaufzeit (WCET).

2013

  • 13-90 Brehmer (2013). Entwurf eines evolutionären Algorithmus zur WCET- und Cache-bewussten Code-Positionierung.

2012

  • 12-90 Hofherr (2012). Low Latency Image Processing With Extensible Processing Platform.

2011

  • 11-80 Kotthaus (2011). Cache-bewusste Code-Positionierung zur Reduktion der maximalen Programmlaufzeit (WCET).

  • 11-90 Risto (2011). Scratchpad-Allokation zur Reduktion der größtmöglichen Laufzeit von Multitask-Systemen.

2010

  • 10-80 Krumme (2010). Dynamische Scratchpad-Allokation von Code und Daten zur WCET-Minimierung.

  • 10-90 Schmitz (2010). ILP-basierte Registerallokation zur Worst-Case Execution Time Minimierung.

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