|Title: Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip. <em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>|
|Written by: Eberle Rambo, Selma Saidi and Rolf Ernst|
|in: January (2016).|
|on pages: 103-108|
|Address: Dresden / Germany|
|how published: 16-95 RSE16 DATE|
Note: ssaidi, ESD
Abstract: Networks-on-Chip (NoCs) are the backbone of Multiprocessor Systems-on-Chip (MPSoCs). In this paper, we perform a formal worst-case communication time analysis of Automatic Repeat reQuest (ARQ) protocols for NoCs. Therefore we integrate the transport layer analysis for general networks and the network layer analysis for NoCs. An ARQ variant optimized for DMA transfers (DMA ARQ) is introduced and analyzed. Experimental evaluation with Stop-and-Wait, Go-Back-N, and DMA ARQ, in the context of real-time memory traffic is presented, including both error-free and error cases. DMA ARQ achieves a factor 6 improvement on latency bounds over conventional Stop-and-Wait.