Prof. Dr. Qiang Li

Email:qiang.li@tuhh.de
Tel: +49 40 42878 3392

Office: Building O (ES38) / Room 4.007

Curriculum Vitae

2025 - now
Professor and head of the Institute of Integrated Circuits and Systems
Hamburg University of Technology (TUHH), Hamburg, Germany

2014 - 2025
Professor and founding head of the Institute of Integrated Circuits and Systems
University of Electronic Science and Technology of China (UESTC), Chengdu, China

2011 - 2014
Associate Professor
Aarhus University, Aarhus, Denmark

2009 - 2011
Professor
University of Electronic Science and Technology of China (UESTC), Chengdu, China

2008 - 2009
Technical Consultant (Staff Design Engineer)
OKI Techno Centre (Singapore), Singapore

2006 - 2008
Engineer / Senior Engineer
Institute of Microelectronics (IME), A-STAR, Singapore

2003 - 2006
Graduate Researcher (PhD Student)
Nanyang Technological University (NTU), Singapore

2001 - 2002
RTP Analog/Mixed-Signal IC Design Engineer
Centre for Wireless Communications (CWC), Singapore

1997 - 2001
Bachelor in Electrical Engineering
Huazhong University of Science and Technology (HUST), Wuhan, China

Academic Services

Distinguished Lecturer, IEEE Solid-State Circuits Society (2020-2021)

ISSCC: TPC (2024-2025), SRP (2015-2020)

CICC: TPC (2021-2025), DC subcomm chair/co-chair (2024-2025)

ESSCIRC: TPC (2018-2023)

ASSCC: TPC (2019-2024)

ICAC (Premier Chinese IC Conference): Co-Founding Chair & TPC (2019- )

Board of Governors (BoG), IEEE Circuits and Systems Society (2021-2022)

ISCAS: Special Sessions (Co-)Chair (2019), Publicity (Co-)Chair (2023), Tutorial (Co-)Chair (2027)

APCCAS: TPC Chair (2018), Steering Committee Chair/Co-Chair (2019- )

PrimeAsia: General Chair (2018)

TCAS-I: Guest Editor (2019)

ASPTC (CASS): member (2018- )

Publications

(Selected only. Full list of publications available at Google Scholar)

  1. X. Chao, Y. Xu, Q. Yu, Z. Zhu, S. Zhang, Q. Li, "A timing-robust 10b 13GS/s ADC with analog fourier transform based frequency interleaving," CICC, Boston, Apr. 2025.

  2. H. Zhuang, Y. Cao, S. Han, S. Liu, Y. Li, R. Sheng, Q. Li, "A chopping-free single-trim bandgap reference using amplifier with PTAT offset," JSSC, early access.

  3. H. Zhuang, Y. Cao, L. Tao, Q. Li, "A 0.69-noise-efficiency-factor 55×-preamp-gain dynamic comparator with a stacking FIA," JSSC, 60(3), Mar. 2025.

  4. Q. Yu, Z. Zhu, C. Liang, Q. Huang, S. Han, F. Tai, R. Yang, S. Wu, Q. Li, "A 12b 3 GS/s passive T/H assisted time-interleaved pipelined SAR ADC with metastability reduction technique and dynamic-bias RA," ASSCC, Hiroshima, Nov. 2024.

  5. W. He, P. Bai, H. Luo, Z. Jin, H. Wu, J. Zhang, X. Chao, H. Liu, Y. He, Q. Li, "131TOPS/W 8b ACIM exploiting weight-embedded auto-accumulation and supporting symmetric quantization networks," CICC, Denver, Apr. 2024.

  6. X. Chao, Q. Li, "A 128-GS/s timing-robust sampling architecture exploiting analog FFT," ISCAS, Monterey, May 2023.

  7. H. Zhuang, N. Sun, L. Tao, Y. Li, Q. Li, "A fully-dynamic kT/C-noise-canceled SAR ADC with trimming-free dynamic amplifier," CICC, San Antonio, Apr. 2023.

  8. H. Zhuang, N. Sun, Y. Cao, L. Tao, Q. Li, "A 0.69-noise-efficiency-factor 4x-current-reuse dynamic comparator with a stacking FIA," CICC, San Antonio, Apr. 2023.

  9. S. Zhang, X. Zhou, C. Gao, Q. Li, “A 130-dB CMRR instrumentation amplifier with common-mode replication,” JSSC, 57(1), Jan. 2022.

  10. P. Zhai, Z. Zhu, X. Zhou, Y. Cai, F. Zhang, Q. Li, "An on-chip power-supply noise analyzer with compressed sensing and enhanced quantization," JSSC, 57(1), Jan. 2022.

  11. Y. Zeng, S. Yang, Y. Liu, Z. Li, W. Huang, X. Huang, X. Zhou, J. Liu, Q. Li, "A 640×512 30μm pixel pitch 1.8 mK-NETD 90.1dB-SNR digital read-out integrated circuit with fully on-chip image algorithm pixel-level calibration," ASSCC, Busan, Nov. 2021.

  12. Q. Yu, X. Zhou, K. Hu, Z. Huang, …, Q. Li, "A 9.08 ENOB 10b 400MS/S subranging SAR ADC with subsetted CDAC and PDAS in 40nm CMOS," ESSCIRC, Grenoble (hybrid), Sept. 6-9, 2021.

  13. X. Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Y.-L. Chung, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Q. Li, M.-F. Chang, “A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips," JSSC, 56(9), Sept. 2021.

  14. S. Zhang, X. Zhou, C. Gao, Q. Li, “An AC-coupled instrumentation amplifier achieving 110-dB CMRR at 50 Hz with chopped pseudoresistors and successive-approximation-based capacitor trimming,” JSSC, 56(1), Jan. 2021.

  15. Z. Zhu, X. Zhou, Y. Du, Y. Feng, Q. Li, "A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration," JSSC, 55(6), June 2020.

  16. P. Zhai, X. Zhou, Y. Cai, Z. Zhu, F. Zhang, Q. Li, “A scalable 20GHz on-die power supply noise analyzer with compressed sensing,” ISSCC, Feb. 2020.

  17. S. Zhang, C. Gao, X. Zhou, Q. Li, “A 130dB-CMRR instrumentation amplifier with common-mode replication,” ISSCC, Feb. 2020.

  18. X. Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Y.-L. Chung, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Q. Li, M.-F. Chang, “A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,” ISSCC, Feb. 2020.

  19. X. Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, Y.-C. Chiu, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Q. Li, M.-F. Chang, “A twin-8T SRAM computation-in-memory unit-macro for multibit CNN based AI edge processors," JSSC, 55(1), Jan. 2020.

  20. Y. Zhao, L. Li, Y. Peng, Q. Li, G. Yang, X. Chuai, Q. Li, G. Han, M. Liu, "Surface potential-based compact model for negative capacitance FETs compatible for logic circuit: with time dependence and multidomain interaction," IEDM, San Francisco, Dec. 2019.

  21. P. Zhai, X. Zhou, Y. Cai, Z. Zhu, F. Zhang, Z. Lin, Q. Li, "A multi-slice VCO-based quantizer for on-chip power supply noise analysis achieving 0.11 (mV)2/sqrt(MHz) noise floor," ASSCC, Nov. 2019.

  22. L. Lv, X. Zhou, Z. Qiao, Q. Li, "Inverter-based subthreshold amplifier techniques and their application in 0.3V ΔƩ-modulators," JSSC, 54(5), May 2019.

  23. Z. Ding, X. Zhou, Q. Li, "A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator," JSSC, 54(4), Apr. 2019. (invited)

  24. X. Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, Y.-C. Chiu, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Q. Li, M.-F. Chang, “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN based machine learning,” ISSCC, Feb. 2019.

  25. L. Lv, A. Jain, X. Zhou, J. Becker, Q. Li, M. Ortmanns, "A 0.4V Gm-C proportional integrator based continuous-time ΔƩ modulator with 50kHz BW and 74.4dB SNDR," JSSC, 53(11), Nov. 2018.

  26. Z. Ding, X. Zhou, Q. Li, "A 0.5-1.1V 10b adaptive bypassing SAR ADC utilizing oscillation cycle information of VCO-based comparator," VLSI-Circuits, Honolulu, June 2018.

  27. H. Chen, X. Zhou, Q. Yu, F. Zhang, Q. Li, "A >3GHz ERBW 1.1-GS/s 8-bit two-step SAR ADC with recursive-weight DAC," VLSI-Circuits, Honolulu, June 2018.

  28. X. Ma, Y. Lu, R. Martins, Q. Li, “A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS,” ISSCC, Feb. 2018.

  29. X. Zhou, Q. Li, S. Kilsgaard, F. Moradi, S. Kappel, P. Kidmose, "A wearable ear-EEG recording system based on dry-contact active electrodes," VLSI-Circuits, Honolulu, June 2016.

  30. J. Gao, G. Li, Q. Li, "An amplifier-free pipeline-SAR ADC architecture with enhanced speed and energy efficiency," TCAS-II, 63(4), Apr. 2016.

  31. C. Liu, Q. Li, Y. Li, X. Li, H. Liu, Y.-Z. Xiong, "An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips," ESSCIRC, Graz, Sept. 2015.

  32. J. Gao, G. Li, Q. Li, "High-speed low-power common-mode insensitive dynamic comparator," EL, 51(2), Jan. 2015.

  33. Z. Qiao, X. Zhou, Q. Li, "A 250mV 77dB DR 10kHz BW SC ΔΣ modulator exploiting subthreshold OTAs," ESSCIRC, Venice, Sept. 2014.

  34. X. Zhou, Q. Li, "A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS," CICC, San Jose, Sept. 2012.

  35. Q. Li, Y. P. Zhang, K. Yeo, W. Lim, "16.6- and 28-GHz fully integrated CMOS RF switches with improved body-floating," TMTT, 56(2), Feb. 2008.

  36. Q. Li, Y. P. Zhang, "A 1.5-V 2−9.6-GHz inductorless low-noise amplifier in 0.13-μm CMOS," TMTT, 55(10), Oct. 2007.

  37. Q. Li, R. Tan, T. Hui, R. Singh, "A 1-V 36-µW low-noise adaptive interface IC for portable biomedical applications," ESSCIRC, Munich, Sept. 2007.

  38. Q. Li, Y. P. Zhang, "CMOS T/R switch design: towards ultra-wideband and higher frequency," JSSC, 42(3), Mar. 2007. (among Singapore’s earliest PhD research published in JSSC)

  39. Q. Li, Y. P. Zhang, J. S. Chang, "An inductorless low-noise amplifier with noise cancellation for UWB receiver front-end," ASSCC, Hangzhou, Nov. 2006.