Head of the Institute

Prof. Dr. Qiang Li

Email:qiang.li(at)tuhh.de
Tel: +49 40 30601 3392

Office: Building O (ES38) / Room 4.007

2025 - now
Professor and head of the Institute of Integrated Circuits and Systems
Hamburg University of Technology (TUHH), Hamburg, Germany
 

2014 - 2025
Professor and founding head of the Institute of Integrated Circuits and Systems
University of Electronic Science and Technology of China (UESTC), Chengdu, China

2011 - 2014
Associate Professor
Aarhus University, Aarhus, Denmark

2009 - 2011
Professor
University of Electronic Science and Technology of China (UESTC), Chengdu, China

2008 - 2009
Technical Consultant (Staff Design Engineer)
OKI Techno Centre (Singapore), Singapore

2006 - 2008
Engineer / Senior Engineer
Institute of Microelectronics (IME), A-STAR, Singapore

2003 - 2006
Graduate Researcher (PhD Student)
Nanyang Technological University (NTU), Singapore

2001 - 2002
RTP Analog/Mixed-Signal IC Design Engineer
Centre for Wireless Communications (CWC), Singapore

1997 - 2001
Bachelor in Electrical Engineering
Huazhong University of Science and Technology (HUST), Wuhan, China

[1] Q. Li, Y. P. Zhang, "CMOS T/R switch design: towards ultra-wideband and higher frequency," JSSC, 42(3), Mar. 2007. (among Singapore’s earliest PhD research published in JSSC)

[2] Q. Li, R. Tan, T. Hui, R. Singh, "A 1-V 36-µW low-noise adaptive interface IC for portable biomedical applications," ESSCIRC, Munich, Sept. 2007.

[3] Q. Li, Y. P. Zhang, "A 1.5-V 2−9.6-GHz inductorless low-noise amplifier in 0.13-μm CMOS," IEEE Trans. Microwave Theory and Tech. (TMTT), 55(10), Oct. 2007.

[4] Q. Li, Y. P. Zhang, K. Yeo, W. Lim, "16.6- and 28-GHz fully integrated CMOS RF switches with improved body-floating," TMTT, 56(2), Feb. 2008.

[5] X. Zhou, Q. Li, "A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS," CICC, San Jose, Sept. 2012.

[6] Z. Qiao, X. Zhou, Q. Li, "A 250mV 77dB DR 10kHz BW SC ΔΣ modulator exploiting subthreshold OTAs," ESSCIRC, Venice, Sept. 2014.

[7] X. Zhou, Q. Li, S. Kilsgaard, F. Moradi, S. Kappel, P. Kidmose, "A wearable ear-EEG recording system based on dry-contact active electrodes," VLSI-Circuits, Honolulu, June 2016.

[8] X. Ma, Y. Lu, R. Martins, Q. Li, “A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS,” ISSCC, Feb. 2018.

[9] H. Chen, X. Zhou, Q. Yu, F. Zhang, Q. Li, "A >3GHz ERBW 1.1-GS/s 8-bit two-step SAR ADC with recursive-weight DAC," VLSI-Circuits, Honolulu, June 2018.

[10] Z. Ding, X. Zhou, Q. Li, "A 0.5-1.1V 10b adaptive bypassing SAR ADC utilizing oscillation cycle information of VCO-based comparator," VLSI-Circuits, Honolulu, June 2018.

[11] L. Lv, A. Jain, X. Zhou, J. Becker, Q. Li, M. Ortmanns, "A 0.4V Gm-C proportional integrator based continuous-time ΔƩ modulator with 50kHz BW and 74.4dB SNDR," JSSC, 53(11), Nov. 2018.

[12] X. Si, …, Q. Li, M.-F. Chang, “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN based machine learning,” ISSCC, Feb. 2019.

[13] Z. Ding, X. Zhou, Q. Li, "A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator," JSSC, 54(4), Apr. 2019. (invited submission)

[14] L. Lv, X. Zhou, Z. Qiao, Q. Li, "Inverter-based subthreshold amplifier techniques and their application in 0.3V ΔƩ-modulators," JSSC, 54(5), May 2019.

[15] P. Zhai, X. Zhou, Y. Cai, Z. Zhu, F. Zhang, Z. Lin, Q. Li, "A multi-slice VCO-based quantizer for on-chip power supply noise analysis achieving 0.11 (mV)2/sqrt(MHz) noise floor," ASSCC, Nov. 2019.

[16] X. Si, …, Q. Li, M.-F. Chang, “A twin-8T SRAM computation-in-memory unit-macro for multibit CNN based AI edge processors," JSSC, 55(1), Jan. 2020.

[17] X. Si, …, Q. Li, M.-F. Chang, “A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,” ISSCC, Feb. 2020.

[18] S. Zhang, C. Gao, X. Zhou, Q. Li, “A 130dB-CMRR instrumentation amplifier with common-mode replication,” ISSCC, Feb. 2020.

[19] P. Zhai, X. Zhou, Y. Cai, Z. Zhu, F. Zhang, Q. Li, “A scalable 20GHz on-die power supply noise analyzer with compressed sensing,” ISSCC, Feb. 2020.

[20] Z. Zhu, X. Zhou, Y. Du, Y. Feng, Q. Li, "A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration," JSSC, 55(6), June 2020.

[21] S. Zhang, X. Zhou, C. Gao, Q. Li, “An AC-coupled instrumentation amplifier achieving 110-dB CMRR at 50 Hz with chopped pseudoresistors and successive-approximation-based capacitor trimming,” JSSC, 56(1), Jan. 2021.

[22] X. Si, …, Q. Li, M.-F. Chang, “A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips," JSSC, 56(9), Sept. 2021.

[23] Q. Yu, X. Zhou, K. Hu, Z. Huang, …, Q. Li, "A 9.08 ENOB 10b 400MS/S subranging SAR ADC with subsetted CDAC and PDAS in 40nm CMOS," ESSCIRC, Grenoble (hybrid), Sept. 6-9, 2021.

[24] P. Zhai, Z. Zhu, X. Zhou, Y. Cai, F. Zhang, Q. Li, "An on-chip power-supply noise analyzer with compressed sensing and enhanced quantization," JSSC, 57(1), Jan. 2022.

[25] S. Zhang, X. Zhou, C. Gao, Q. Li, “A 130-dB CMRR instrumentation amplifier with common-mode replication,” JSSC, 57(1), Jan. 2022.

[26] H. Zhuang, Y. Cao, L. Tao, Q. Li, "A 0.69-noise-efficiency-factor 55×-preamp-gain dynamic comparator with a stacking FIA," JSSC, 60(3), Mar. 2025.