[176880]
Title: Approximate Adder Structures on FPGAs. <em>In Proceedings of the Workshop on Approximate Computing (AC)</em>
Written by: Andreas Becher, Jorge Echavarria, Daniel Ziener and J&uuml;rgen Teich
in: October (2015).
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Address: Paderborn / Germany
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how published: 15-30 BEZT15 AC
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[BibTex]

Note: dziener, ESD

Abstract: In this paper, we propose novel approximate adder structures for FPGA-based implementations. These adder structures take advantage of the available FPGA resources. Compared with a full featured accurate adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structures, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.