Timing Analysis on Code-Level (TACLe)
|Name||Timing Analysis on Code-Level|
|Role of TUHH||Action Vice Chair, member of Working Groups 1, 2 and 4|
|Funds Donor||COST Office Brussels|
TACLe is a four years lasting COST Action funded by the COST Office in Brussels.
Many embedded systems are safety-critical real-time systems that must process data within given deadlines. To validate real-time properties, timing analyses of program code are mandatory. Research on techniques for timing analysis of software touches many areas within computer science, e.g., computer architecture, compiler construction and formal verification.
This COST Action aims to cross-link the leading European researchers in these areas and thus to strengthen Europe's leading position in the field of timing analysis. TACLe's research activities include timing models for multicore systems, support of timing analysis by software development tools, early-stage timing analysis right in the beginning of the software development cycle, and the consideration of resources other than time like, e.g., energy dissipation.
TACLe Publications of the Embedded Systems Design Group
|Title: Static analysis of multi-core TDMA resource arbitration delays.|
|Written by: Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury|
|in: <em>the International Journal of Time-Critical Computing Systems (Real-Time Systems)</em>. March (2014).|
|Volume: <strong>50</strong>. Number: (2),|
|on pages: 185-229|
|how published: 14-70 KFM+14 RTS|
Note: hfalk, ESD, emp2, tacle, WCC
Abstract: In the development of hard real-time systems, knowledge of the Worst-Case Execution Time (WCET) is needed to guarantee the safety of a system. For single-core systems, static analyses have been developed which are able to derive guaranteed bounds on a program's WCET. Unfortunately, these analyses cannot directly be applied to multi-core scenarios, where the different cores may interfere with each other during the access to shared resources like for example shared buses or memories. For the arbitration of such resources, TDMA arbitration has been shown to exhibit favorable timing predictability properties. In this article, we review and extend a methodology for analyzing access delays for TDMA-arbitrated resources. Formal proofs of the correctness of these methods are given and a thorough experimental evaluation is carried out, where the presented techniques are compared to preexisting ones on an extensive set of real-world benchmarks for different classes of analyzed systems.