|Title: A LUT-Based Approximate Adder. <em>In Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)</em>|
|Written by: Andreas Becher, Jorge Echavaria, Daniel Ziener, Stefan Wildermann and Jürgen Teich|
|in: May (2016).|
|Address: Washington DC / USA|
|how published: 16-65 BEZWT16 FCCM|
Note: dziener, ESD
Abstract: In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.