2015
Thole N,
Fey G,
Garcia-Ortiz A.
Analyzing an SET at Gate Level using a Conservative Approach.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2015.
Thole N,
Riener H,
Fey G.
Equivalence Checking on System Level using A Priori Knowledge.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2015.
p. 177-182.
Flenker T,
Sülflow A,
Fey G.
Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation.. In:
Asian Test Symposium (ATS).
2015.
p. 145-150.
Ytterdal T,
Aunet S,
Chairs G,
Larsen BB,
(editors) GF.
European Conference on Circuit Theory and Design (ECCTD).
2015.
2014
Finder A,
Sülflow A,
Fey G.
Latency Analysis for Sequential Circuits..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2014;
643-647.
[DOI]
Treudler CJ,
Schröder J,
Greif F,
Stohlmann K,
Aydos G,
Fey G.
Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions.. In:
Data Systems In Aerospace (DASIA).
2014.
Lüdtke D,
Westerdorff K,
Stohlmann K,
Börner A,
Maibaum O,
Peng T,
Weps B,
Fey G,
Gerndt A.
OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft.. In:
IEEE Aerospace Conference (AEROCONF).
2014.
TODO
Fey G.
Command and Data Handling Infrastructure for Space Systems (Invited Talk).. In:
IEEE Int'l Symposium on Multi-Valued Logic (ISMVL).
2014.
Riener H,
Soeken M,
Werther C,
Fey G,
Drechsler R.
metaSMT: A Unified Interface to SMT-LIB2.. In:
Forum on Specification and Design Languages (FDL).
2014.
Riener H,
Keszocze O,
Drechsler R,
Fey G.
A Logic for Cardinality Constraints (Extended Abstract).. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
2014.
p. 217-220.
Malburg J,
Finder A,
Fey G.
A Simulation Based Approach for Automated Feature Localization..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2014;
1886-1899.
[DOI]
Malburg J,
Encrenaz-Tiphene E,
Fey G.
Mutation based Feature Localization.. In:
International Workshop on Microprocessor Test and Verification (MTV).
2014.
p. 49-54.
Malburg J,
Encrenaz-Tiphene E,
Fey G.
Mutation based Feature Localization.. In:
Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
2014.
Malburg J,
Krafczyk N,
Fey G.
Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2014.
Borchers K,
Fey G,
Luedtke D.
Automatic Performance Tracking of a SpaceWire Network.. In:
International SpaceWire Conference.
2014.
Dehbashi M,
Fey G.
Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2014.
Dehbashi M,
Fey G.
SAT-Based Speedpath Debugging Using Waveforms.. In:
IEEE European Test Symposium (ETS).
2014.
p. 63-68.
Dehbashi M,
Fey G.
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs.. In:
Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP).
2014.
p. 400-404.
[DOI]
Dehbashi M,
Fey G.
Debug Automation for Synchronization Bugs at RTL.. In:
VLSI Design Conference.
2014.
p. 44-49.
[DOI]
Thole N,
Fey G.
Equivalence Checking on System Level using Stepwise Induction.. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
2014.
p. 197-200.
Eggersglüß S,
Fey G,
Polian I.
Test digitaler Schaltkreise..
De Gruyter Oldenbourg;
2014.
2013
Finder A,
Witte J,
Fey G.
Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2013.
p. 60-65.
Große D,
Fey G,
Drechsler R.
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis..
Electronic Communications of the EASST..
2013;
13 pages.
[DOI]
TODO