2015
Thole N,
Fey G,
Garcia-Ortiz A.
Analyzing an SET at Gate Level using a Conservative Approach.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2015.
Thole N,
Riener H,
Fey G.
Equivalence Checking on System Level using A Priori Knowledge.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2015.
p. 177-182.
Flenker T,
Sülflow A,
Fey G.
Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation.. In:
Asian Test Symposium (ATS).
2015.
p. 145-150.
Ytterdal T,
Aunet S,
Chairs G,
Larsen BB,
(editors) GF.
European Conference on Circuit Theory and Design (ECCTD).
2015.