2005
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FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC..
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Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits.. In:
IEEE Int'l Conference on ASIC (ASICON).
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SyCE: An Integrated Environment for System Design in SystemC.. In:
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Utilizing Don't Care States in SAT-based Bounded Sequential Problems.. In:
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Controlling the Memory During Manipulation of Word-Level Decision Diagrams.. In:
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2005.
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ParSyC: An Efficient SystemC Parser.. In:
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BDD Circuit Optimization for Path Delay Fault Testability.. In:
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Improving Simulation-Based Verification by Means of Formal Methods.. In:
ASP Design Automation Conference (ASPDAC).
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Visualization of Diagnosis Results for Design Debugging.. In:
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Algorithms for Taylor Expansion Diagrams.. In:
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Cost-efficient Block Verification for a UMTS Up-link Chip-rate Coprocessor.. In:
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2004.
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Disjoint Sum of Product Minimization by Evolutionary Algorithms.. In:
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Design Understanding by Automatic Property Generation.. In:
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Synthesis of Fully Testable Circuits from BDDs..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
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2003
Große D,
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Modeling Multi-Valued Circuits in SystemC.. In:
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BDD Circuit Optimization for Path Delay Fault-Testability.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
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A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization.. In:
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2003.
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Finding Good Counter-Examples to Aid Design Verification.. In:
ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE).
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Fey G,
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Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques.. In:
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2003.
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