2012
Dehbashi M,
Fey G.
Automated Post-Silicon Debugging of Failing Speedpaths.. In:
Asian Test Symposium (ATS).
2012.
p. 13-18.
Dehbashi M,
Fey G.
Application of Timing Variation Modeling to Speedpath Diagnosis.. In:
System, Software, SoC and Silcon Debug Conference (S4D).
2012.
p. 34-37.
Dehbashi M,
Fey G.
Automated Debugging from Pre-Silicon to Post-Silicon.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2012.
p. 324-329.
Dehbashi M,
Fey G,
Roy K,
Raghunathan A.
On Modeling and Evaluation of Logic Circuits Under Timing Variations.. In:
EUROMICRO Symposium on Digital System Design (DSD).
2012.
p. 431-436.
Dehbashi M,
Fey G,
Roy K,
Raghunathan A.
Functional Analysis of Circuits Under Timing Variations.. In:
edaWorkshop.
2012.
p. 45-50.
Dehbashi M,
Fey G,
Roy K,
Raghunathan A.
Functional Analysis of Circuits Under Timing Variations.. In:
IEEE European Test Symposium (ETS).
2012.
p. 177.
2011
Finder A,
Sülflow A,
Fey G.
Latency Analysis for Sequential Circuits.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2011.
p. 119-124.
Finder A,
Sülflow A,
Fey G.
Latency Analysis for Sequential Circuits.. In:
IEEE European Test Symposium (ETS).
2011.
p. 129-134.
[DOI]
Große D,
Fey G,
Drechsler R.
Enhanced Formal Verification Flow for Circuits Integrating Debugging.. In:
Design and Test Technology for Dependable Systems-on-Chip.
Information Science Reference;
2011.
p. 119-129.
Haedicke F,
Frehse S,
Fey G,
Große D,
Drechsler R.
metaSMT: Focus on Your Application not on Solver Integration.. In:
Int'l Workshop on Design and Implementation of Formal Tools and Systems (DIFTS).
2011.
p. 22-29.
Fey G.
Assessing System Vulnerability using Formal Verification Techniques.. In:
Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS).
2011.
Fey G.
Orchestrated Multi-Level Information Flow Analysis to Understand SoCs.. In:
Design Automation Conference (DAC).
2011.
p. 284-285.
Fey G,
Sülflow A,
Frehse S,
Drechsler R.
Effective Robustness Analysis using Bounded Model Checking Techniques..
IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)..
2011;
1239-1252.
[DOI]
Riener H,
Bloem R,
Fey G.
Test Case Generation from Mutants using Model Checking Techniques.. In:
Mutation.
2011.
p. 388-397.
Soeken M,
Kühne U,
Freibothe M,
Fey G,
Drechsler R.
Towards Automatic Property Generation for the Formal Verification of Bus Bridges.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2011.
p. 417-422.
Soeken M,
Kühne U,
Freibothe M,
Fey G,
Drechsler R.
Towards Automatic Property Generation for the Formal Verification of Bus Bridges.. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
2011.
Dehbashi M,
Sülflow A,
Fey G.
Automated Design Debugging in a Testbench-Based Verification Environment.. In:
EUROMICRO Symposium on Digital System Design (DSD).
2011.
p. 479-486.
Dehbashi M,
Fey G.
Automated Post-Silicon Debugging of Design Bugs.. In:
System, Software, SoC and Silcon Debug Conference (S4D).
2011.
p. 67-71.
Frehse S,
Haedicke F,
Diepenbeck M,
Fey G,
Drechsler R.
Hochoptimierter Ablauf zur Robustheitsprüfung.. In:
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE).
2011.
p. 35-42.
2010
Finder A,
Fey G.
Evaluating Debugging Algorithms from a Qualitative Perspective.. In:
Int'l Workshop on Boolean Problems (IWSBP).
2010.
Finder A,
Fey G.
Evaluating Debugging Algorithms from a Qualitative Perspective.. In:
Forum on Specification and Design Languages (FDL).
2010.
Sülflow A,
Fey G,
Drechsler R.
Bounded Fault Tolerance Checking (Invited Talk).. In:
Forum on Specification and Design Languages (FDL).
2010.
Sülflow A,
Fey G,
Drechsler R.
Using QBF to Increase Accuracy of SAT-Based Debugging.. In:
IEEE Int'l Symposium on Circuits and Systems (ISCAS).
2010.
p. 641-644.
Haedicke F,
Alizadeh B,
Fey G,
Fujita M,
Drechsler R.
Polynomial Datapath Optimization using Constraint Solving and Formal Modelling.. In:
IEEE/ACM Int'l Conf. on CAD (ICCAD).
2010.
p. 756-761.
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