2016
Aydos G,
Fey G.
Exploiting Error Detection Latency for Parity-based Soft Error Detection.. In:
IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS).
2016.
[DOI]
Riener H,
Haedicke F,
Frehse S,
Soeken M,
Große D,
Drechsler R,
Fey G.
metaSMT: Focus On Your Application And Not On Solver Integration..
International Journal on Software Tools for Technology Transfer (STTT)..
2016;
1-17.
[DOI]
Riener H,
Fey G.
Exact Diagnosis using Boolean Satisfiability.. In:
IEEE/ACM Int'l Conf. on CAD (ICCAD).
2016.
p. 53:1-53:8.
[DOI]
Riener H,
Fey G.
Counterexample-Guided Diagnosis.. In:
International Verification and Security Workshop (IVSW).
2016.
TODO
Harris I,
Ray S,
Fey G,
Soeken M.
Multilevel Design Understanding: From Specification to Logic.. In:
IEEE/ACM Int'l Conf. on CAD (ICCAD).
2016.
Malburg J,
Finder A,
Fey G.
Debugging hardware designs using dynamic dependency graphs..
Microprocessors and Microsystems (MICPRO)..
2016;
347-359.
Malburg J,
Flenker T,
Fey G.
Generating Good Properties from a Small Number of Use Cases.. In:
International Verification and Security Workshop (IVSW).
2016.
Meß J,
Schmidt R,
Fey G,
Dannemann F.
On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms.. In:
ESA International Tracking, Telemetry and Command Systems for Space Applications (TTC).
2016.
Thole N,
Riener H,
Fey G.
Equivalence Checking on ESL Utilizing A Priori Knowledge.. In:
Forum on Specification and Design Languages (FDL).
2016.
Thole N,
Anghel L,
Fey G.
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.. In:
IEEE Annual Symposium on VLSI (ISVLSI).
2016.
p. 278-283.
[DOI]
Thole N,
Anghel L,
Fey G.
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits (extended abstract).. In:
IEEE European Test Symposium (ETS).
2016.
p. 2.
[DOI]
Thole N,
Anghel L,
Fey G.
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.. In:
GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ).
2016.
Krafczyk N,
Riener H,
Fey G.
WCET Overapproximation for Software in the Context of a Cyber-Physical System.. In:
IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC).
2016.
Avramenko S,
Reorda MS,
Violante M,
Fey G.
Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables.. In:
IEEE Latin-American Test Symposium (LATS).
2016.
p. 14-19.
[DOI]
Avramenko S,
Reorda MS,
Violante M,
Fey G,
Meß J,
Schmidt R.
On the robustness of compression algorithms for space applications.. In:
IEEE International On-Line Testing Symposium (IOLTS).
2016.
Flenker T,
Fey G.
Matching Abstract and Concrete Hardware Models for Design Understanding.. In:
Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
2016.
2015
TODO
Aydos G,
Fey G.
Empirical Results on Parity-based Soft Error Detection with Software-based Retry.. In:
IEEE Nordic Circuits and Systems Conference (NORCAS).
2015.
Riener H,
Thomsen MK,
Fey G.
Execution Tracing of C Code for Formal Analysis (Extended Abstract).. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
2015.
p. 160-164.
Riener H,
Ehlers R,
Fey G.
Path-Based Program Repair.. In:
International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS.
2015.
p. 22-32.
Martinez J,
Malburg J,
Ziadi T,
Fey G.
Towards analysing feature locations through testing traces with BUT4Reuse.. In:
Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
2015.
p. 10-15.
Dehbashi M,
Fey G.
Transaction-based online debug for NoC-based multiprocessor SoCs..
Microprocessors and Microsystems (MICPRO)..
2015;
157-166.
[DOI]
Dehbashi M,
Fey G.
Debug Automation from Pre-Silicon to Post-Silicon..
Springer;
2015.
p. 171.
Thole N,
Fey G,
Garcia-Ortiz A.
Conservatively Analyzing Transient Faults.. In:
IEEE Annual Symposium on VLSI (ISVLSI).
2015.
p. 50-55.