Institute of Embedded Systems

Fey G, Drechsler R. Self-Explaining Digital Systems - Some Technical Steps.. In: ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). 2019.

Bloem R, Fey G, Greif F, Könighofer R, Pill I, Riener H, Röck F. Synthesizing Adaptive Test Strategies from Temporal Logic Specifications.. Formal Methods in System Design (FMSD).. 2019;      [DOI] 

Ghasempouri T, Malburg J, Danese A, Pravadelli G, Fey G, Raik J. Engineering of an Effective Automatic Dynamic Assertion Mining Platform.. In: IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC). 2019.      [DOI] 

Ghasempouri T, Malburg J, Danese A, Pravadelli G, Fey G, Raik J. Engineering of an Effective Automatic Assertion-based Verification Platform.. In: Workshop on Design Automation for Understanding Hardware Designs (DUHDe). 2019.

Tibebu AT, Fey G. Augmenting All Solutions SAT Solving for Circuits with Structural Information.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2018.

Gianluca Martino HR, Fey G. Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems.. In: In Proceedings of International Workshop on Logic & Synthesis (IWLS). San Francisco / USA: 2018 Jul..

Görschwin Fey JR, Riener H. Design Understanding: From Logic to Specification.. In: In Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). Verona / Italy: 2018.      [DOI] 

Malburg J, Riener H, Fey G. Mining Latency Guarantees for RTL Designs.. In: IEEE Int'l Symposium on Multi-Valued Logic (ISMVL). 2018.

Janson K, Treudler CJ, Hollstein T, Raik J, Jenihhin M, Fey G. Software-Level TMR Approach for On-Board Data Processing in Space Applications.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2018.

Aydos G, Fey G. Empirical Results on Parity-based Soft Error Detection with Software-based Retry.. Microprocessors and Microsystems (MICPRO).. 2017; 62-68.      [DOI] 

Riener H, Fey G. Computing Exact Fault Candidates Incrementally.. In: Workshop on Design Automation for Understanding Hardware Designs (DUHDe). 2017.

Riener H, Koenighofer R, Fey G, Bloem R. SMT-Based CPS Parameter Synthesis.. In: Applied Verification for Continuous and Hybrid Systems (ARCH). 2017. p. 126-133.

Riener H, Ehlers R, Fey G. CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification.. In: ASP Design Automation Conference (ASPDAC). 2017. p. 251-256.

Riener H, Ehlers R, Fey G. Counterexample-Guided EF Synthesis of Boolean Functions.. In: ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). 2017.

Malburg J, Riener H, Fey G. Mining Latency Guarantees for RT-level Designs.. In: Workshop on Design Automation for Understanding Hardware Designs (DUHDe). 2017.

Malburg J, Flenker T, Fey G. Property Mining using Dynamic Dependency Graphs.. In: ASP Design Automation Conference (ASPDAC). 2017. p. 244-250.

Meß J, Schmidt R, Fey G. Adaptive Compression Schemes for Housekeeping Data.. In: IEEE Aerospace Conference (AEROCONF). 2017.

Thole N, Fey G. Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability.. In: GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ). 2017.

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Schmidt R, Garcia-Ortiz A, Fey G. Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.. In: IEEE International On-Line Testing Symposium (IOLTS). 2017. p. 240-243.      [DOI] 

Avramenko S, Reorda MS, Violante M, Fey G. A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.. Journal of Electronic Testing: Theory and Applications (JETTA).. 2017; 53-64.      [DOI] 

Flenker T, Fey G. Mapping Abstract and Concrete Hardware Models for Design Understanding.. In: IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 2017.

Flenker T, Malburg J, Fey G, Avramenko S, Violante M, Reorda MS. Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.. In: IEEE Annual Symposium on VLSI (ISVLSI). 2017.

Aleksandrowicz G, Arbel E, Bloem R, Braak T, Devadze S, Fey G, Jenihhin M, Jutman A, Kerkhoff HG, Könighofer R, Malburg J, Moran S, Raik J, Rauwerda G, Riener H, Röck F, Shibin K, Sunesen K, Wan J, Zhao Y. Designing Reliable Cyber-Physical Systems.. In: Forum on Specification and Design Languages (FDL). 2016.

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