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  • 21-999 BKF:2021b MOCAST (2021). Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference.

  • 21-999 GBE+:2021 ATS (2021). Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining.

  • 21-999 MBE+:2021 DSD_EUROMICRO (2021). Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems.

  • 21-999 PMF:2021 DSD_EUROMICRO (2021). Metrics for the Evaluation of Approximate Sequential Streaming Circuits.

  • 21-999 PSF:2021b MBMV (2021). Extended Abstract: Viability of Decision Trees for Learning Models of Systems.

  • 21-999 PSH+:2021 LEAC (2021). Automata Learning for Automated Test Generation of Real Time Localization Systems.

  • 21-999 SPBF:2021 SE4ICPS (2021). Learning Models of Cyber-Physical Systems using Automata Learning.

(2020).

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(2019).

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  • 19-999 BFG+:2019 FMSD (2019). Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. Formal Methods in System Design (FMSD).

  • 19-999 FD:2019b MBMV (2019). Self-Explaining Digital Systems - Some Technical Steps.

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  • 19-999 FG:2019 ETS (2019). Symbolic Circuit Analysis under an Arc Based Timing Model.

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  • 19-999 GMD+:2019b DUHDE (2019). Engineering of an Effective Automatic Assertion-based Verification Platform.

  • 19-999 MF:2019 FDL (2019). Syntax-Guided Enumeration of Temporal Properties.

  • 19-999 MRF:2019 DUHDE (2019). Complete Specification Mining.

(2018).

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(2017).

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  • 17-999 ASVF:2017 JETTA (2017). A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. Journal of Electronic Testing: Theory and Applications (JETTA). 53-64

  • 17-999 FF:2017 DDECS (2017). Mapping Abstract and Concrete Hardware Models for Design Understanding.

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  • 17-999 MRF:2017 DUHDE (2017). Mining Latency Guarantees for RT-level Designs.

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  • 17-999 REF:2017 ASPDAC (2017). CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification. 251-256

  • 17-999 REF:2017b MBMV (2017). Counterexample-Guided EF Synthesis of Boolean Functions.

  • 17-999 RF:2017b DUHDE (2017). Computing Exact Fault Candidates Incrementally.

  • 17-999 RKFB:2016 ARCH (2017). SMT-Based CPS Parameter Synthesis. 126-133

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  • 17-999 TF:2017 TUZ (2017). Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability.

(2016).

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  • 16-999 FF:2016 DUHDE (2016). Matching Abstract and Concrete Hardware Models for Design Understanding.

  • 16-999 FHRS:2016 ICCAD (2016). Multilevel Design Understanding: From Specification to Logic.

  • 16-999 FR:2016 FDL (2016). Designing Reliable Cyber-Physical Systems.

  • 16-999 HRFS:2016b ICCAD (2016). Multilevel Design Understanding: From Specification to Logic (Special Session).

  • 16-999 KRF:2016 VLSISOC (2016). WCET Overapproximation for Software in the Context of a Cyber-Physical System.

  • 16-999 MFF:2016 MICPRO (2016). Debugging hardware designs using dynamic dependency graphs. Microprocessors and Microsystems (MICPRO). 347-359

  • 16-999 MFF:2016b IVSW (2016). Generating Good Properties from a Small Number of Use Cases.

  • 16-999 MSFD:2016 TTC (2016). On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms.

  • 16-999 RF:2016 ICCAD (2016). Exact Diagnosis using Boolean Satisfiability. 53:1-53:8

  • 16-999 RF:2016c IVSW (2016). Counterexample-Guided Diagnosis.

  • 16-999 RHF+:2016 STTT (2016). metaSMT: Focus On Your Application And Not On Solver Integration. International Journal on Software Tools for Technology Transfer (STTT). 1-17

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  • 16-999 TRF:2016 FDL (2016). Equivalence Checking on ESL Utilizing A Priori Knowledge.

(2015).

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  • 15-999 DF:2015 MICPRO (2015). Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocessors and Microsystems (MICPRO). 157-166

  • 15-999 EF:2015 (2015). Workshop on Design Automation for Understanding Hardware Designs (DUHDe).

  • 15-999 FSF:2015 ATS (2015). Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation. 145-150

  • 15-999 MMZF:2015 DUHDE (2015). Towards analysing feature locations through testing traces with BUT4Reuse. 10-15

  • 15-999 REF:2015 FESCA (2015). Path-Based Program Repair. 22-32

  • 15-999 RKF:2015 MBMV (2015). Execution Tracing of C Code for Formal Analysis (Extended Abstract). 160-164

  • 15-999 TFG:2015 ISVLSI (2015). Conservatively Analyzing Transient Faults. 50-55

  • 15-999 TFG:2015b TUZ (2015). Analyzing an SET at Gate Level using a Conservative Approach.

  • 15-999 TRF:2015 DDECS (2015). Equivalence Checking on System Level using A Priori Knowledge. 177-182

  • 15-999 YA+:2015 ECCTD (2015). 22nd European conference on circuit theory and design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015.

(2014).

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  • 14-999 DF:2014b VLSIDC (2014). Debug Automation for Synchronization Bugs at RTL. 44-49

  • 14-999 DF:2014c PDP (2014). Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. 400-404

  • 14-999 DF:2014d ETS (2014). SAT-Based Speedpath Debugging Using Waveforms. 63-68

  • 14-999 DF:2014f TUZ (2014). Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms.

  • 14-999 EF:2014 (2014). Workshop on Design Automation for Understanding Hardware Designs (DUHDe).

  • 14-999 EFP:2014 (2014). Test digitaler Schaltkreise.

  • 14-999 Fey:2014 ISMVL (2014). Command and Data Handling Infrastructure for Space Systems (Invited Talk).

  • 14-999 FSF:2014 TCAD (2014). Latency Analysis for Sequential Circuits. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 643-647

  • 14-999 LWS+:2014 AEROCONF (2014). OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft.

  • 14-999 MEF:2014 MTV (2014). Mutation based Feature Localization. 49-54

  • 14-999 MEF:2014b DUHDE (2014). Mutation based Feature Localization.

  • 14-999 MFF:2014 TCAD (2014). A Simulation Based Approach for Automated Feature Localization. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1886-1899

  • 14-999 MKF:2014 DDECS (2014). Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques.

  • 14-999 RKDF:2014 MBMV (2014). A Logic for Cardinality Constraints (Extended Abstract). 217-220

  • 14-999 RSW+:2014 FDL (2014). metaSMT: A Unified Interface to SMT-LIB2.

  • 14-999 TF:2014 MBMV (2014). Equivalence Checking on System Level using Stepwise Induction. 197-200

  • 14-999 TSG+:2014 DASIA (2014). Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions.

(2013).

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  • 13-999 DF:2013 DT (2013). Debug Automation for Logic Circuits Under Timing Variations. IEEE Design and Test of Computers (DT). 60-69

  • 13-999 DF:2013c DDECS (2013). Efficient Automated Speedpath Debugging. 48-53

  • 13-999 DF:2013e TUZ (2013). Towards Debug Automation for Timing Bugs at RTL.

  • 13-999 DSF:2013 MICPRO (2013). Automated Design Debugging in a Testbench-Based Verification Environment. Microprocessors and Microsystems (MICPRO). 206-217

  • 13-999 FS:2013 DATE (2013). Reliability Analysis Reloaded: How Will We Survive? (Embedded Tutorial).

  • 13-999 FWF:2013 DDECS (2013). Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications. 60-65

  • 13-999 GFD:2013 ECEASST (2013). Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electronic Communications of the EASST. 13 pages

  • 13-999 MFF:2013 DATE (2013). Tuning Dynamic Data Flow Analysis to Support Design Understanding. 1179-1184

  • 13-999 MFF:2013b ZUE (2013). Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns. 59-66

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