2018

  • Karl Janson and Carl Johann Treudler and Thomas Hollstein and Jaan Raik and Maksim Jenihhin and Goerschwin Fey.
    Software-Level TMR Approach for On-Board Data Processing in Space Applications.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2018.


  • Gianluca Martino and Heinz Riener and Goerschwin Fey.
    Coverage-Guided CTL Property Enumeration for Design Understanding of Sequential Systems.
    Int'l Workshop on Logic Synthesis (IWLS), 2018.


  • Jan Malburg and Heinz Riener and Goerschwin Fey.
    Mining Latency Guarantees for RTL Designs.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), 2018.


  • Abraham Temesgen Tibebu and Goerschwin Fey.
    Augmenting All Solutions SAT Solving for Circuits with Structural Information.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2018.


2017

  • Gökçe Aydos and Goerschwin Fey.
    Empirical Results on Parity-based Soft Error Detection with Software-based Retry.
    In Microprocessors and Microsystems (MICPRO), pages 62-68, 2017.
    [doi: 10.1016/j.micpro.2016.09.009]

  • Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey.
    A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.
    In Journal of Electronic Testing: Theory and Applications (JETTA), pages 53-64, 2017.
    [doi: 10.1007/s10836-016-5637-6]

  • Tino Flenker and Goerschwin Fey.
    Mapping Abstract and Concrete Hardware Models for Design Understanding.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2017.


  • Tino Flenker and Jan Malburg and Görschwin Fey and Serhiy Avramenko and Massimo Violante and Matteo Sonza Reorda.
    Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.
    IEEE Annual Symposium on VLSI (ISVLSI), 2017.


  • Jan Malburg and Tino Flenker and Goerschwin Fey.
    Property Mining using Dynamic Dependency Graphs.
    ASP Design Automation Conference (ASPDAC), pages 244-250, 2017.


  • Jan Malburg and Heinz Riener and Goerschwin Fey.
    Mining Latency Guarantees for RT-level Designs.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2017.


  • Meß, Jan-Gerd and Schmidt, Robert and Fey, Goerschwin.
    Adaptive Compression Schemes for Housekeeping Data.
    IEEE Aerospace Conference (AEROCONF), 2017.


  • Heinz Riener and Rüdiger Ehlers and Goerschwin Fey.
    CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification.
    ASP Design Automation Conference (ASPDAC), pages 251-256, 2017.


  • Heinz Riener and Ruediger Ehlers and Goerschwin Fey.
    Counterexample-Guided EF Synthesis of Boolean Functions.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017.


  • Heinz Riener and Goerschwin Fey.
    Computing Exact Fault Candidates Incrementally.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2017.


  • Heinz Riener and Robert Koenighofer and Goerschwin Fey and Roderick Bloem.
    SMT-Based CPS Parameter Synthesis.
    Applied Verification for Continuous and Hybrid Systems (ARCH), pages 126-133, 2017.


  • Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey.
    Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.
    IEEE International On-Line Testing Symposium (IOLTS), pages 240-243, 2017.
    [doi: 10.1109/IOLTS.2017.8046245]

  • Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey.
    Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.
    IEEE International On-Line Testing Symposium (IOLTS), 2017.


  • Niels Thole and Goerschwin Fey.
    Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2017.


2016

  • Gadi Aleksandrowicz and Eli Arbel and Roderick Bloem and Timon ter Braak and Sergei Devadze and Goerschwin Fey and Maksim Jenihhin and Artur Jutman and Hans G. Kerkhoff and Robert Könighofer and Jan Malburg and Shiri Moran and Jaan Raik and Gerard Rauwerda and Heinz Riener and Franz Röck and Konstantin Shibin and Kim Sunesen and Jinbo Wan and Yong Zhao.
    Designing Reliable Cyber-Physical Systems.
    Forum on Specification and Design Languages (FDL), 2016.


  • Gökçe Aydos and Goerschwin Fey.
    Exploiting Error Detection Latency for Parity-based Soft Error Detection.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2016.
    [doi: 10.1109/DDECS.2016.7482440]

  • Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey and Jan-Gerd Meß and Robert Schmidt.
    On the robustness of compression algorithms for space applications.
    IEEE International On-Line Testing Symposium (IOLTS), 2016.


  • Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey.
    Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables.
    IEEE Latin-American Test Symposium (LATS), pages 14-19, 2016.
    [doi: 10.1109/LATW.2016.7483332]

  • Tino Flenker and Goerschwin Fey.
    Matching Abstract and Concrete Hardware Models for Design Understanding.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2016.


  • Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken.
    Multilevel Design Understanding: From Specification to Logic.
    IEEE/ACM Int'l Conf. on CAD (ICCAD), 2016.


  • Goerschwin Fey and Jaan Raik (Organizers).
    Designing Reliable Cyber-Physical Systems.
    Forum on Specification and Design Languages (FDL), 2016.


  • Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken.
    Multilevel Design Understanding: From Specification to Logic (Special Session).
    IEEE/ACM Int'l Conf. on CAD (ICCAD), 2016.


  • Niklas Krafczyk and Heinz Riener and Goerschwin Fey.
    WCET Overapproximation for Software in the Context of a Cyber-Physical System.
    IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC), 2016.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Debugging hardware designs using dynamic dependency graphs.
    In Microprocessors and Microsystems (MICPRO), pages 347-359, 2016.


  • Jan Malburg and Tino Flenker and Goerschwin Fey.
    Generating Good Properties from a Small Number of Use Cases.
    International Verification and Security Workshop (IVSW), 2016.


  • Jan-Gerd Meß and Robert Schmidt and Goerschwin Fey and Frank Dannemann.
    On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms.
    ESA International Tracking, Telemetry and Command Systems for Space Applications (TTC), 2016.


  • Heinz Riener and Goerschwin Fey.
    Exact Diagnosis using Boolean Satisfiability.
    IEEE/ACM Int'l Conf. on CAD (ICCAD), pages 53:1-53:8, 2016.
    [doi: 10.1145/2966986.2967036]

  • Heinz Riener and Goerschwin Fey.
    Counterexample-Guided Diagnosis.
    International Verification and Security Workshop (IVSW), 2016.


  • Heinz Riener and Finn Haedicke and Stefan Frehse and Mathias Soeken and Daniel Große and Rolf Drechsler and Goerschwin Fey.
    metaSMT: Focus On Your Application And Not On Solver Integration.
    In International Journal on Software Tools for Technology Transfer (STTT), pages 1-17, 2016.
    [doi: 10.1007/s10009-016-0426-1]

  • Niels Thole and Lorena Anghel and Goerschwin Fey.
    A Hybrid Algorithm to Conservatively Check the Robustness of Circuits (extended abstract).
    IEEE European Test Symposium (ETS), pages 2, 2016.
    [doi: 10.1109/ETS.2016.7519326]

  • Niels Thole and Lorena Anghel and Goerschwin Fey.
    A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.
    IEEE Annual Symposium on VLSI (ISVLSI), pages 278-283, 2016.
    [doi: 10.1109/ISVLSI.2016.106]

  • Niels Thole and Lorena Anghel and Goerschwin Fey.
    A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2016.


  • Niels Thole and Heinz Riener and Goerschwin Fey.
    Equivalence Checking on ESL Utilizing A Priori Knowledge.
    Forum on Specification and Design Languages (FDL), 2016.


2015

  • Gökçe Aydos and Goerschwin Fey.
    Empirical Results on Parity-based Soft Error Detection with Software-based Retry.
    IEEE Nordic Circuits and Systems Conference (NORCAS), 2015.


  • Mehdi Dehbashi and Goerschwin Fey.
    Debug Automation from Pre-Silicon to Post-Silicon.
    pages 171, 2015.


  • Mehdi Dehbashi and Goerschwin Fey.
    Transaction-based online debug for NoC-based multiprocessor SoCs.
    In Microprocessors and Microsystems (MICPRO), pages 157-166, 2015.
    [doi: http://dx.doi.org/10.1016/j.micpro.2015.03.003]

  • Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers).
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
    2015.


  • Tino Flenker and André Sülflow and Goerschwin Fey.
    Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation.
    Asian Test Symposium (ATS), pages 145-150, 2015.


  • Jabier Martinez and Jan Malburg and Tewfik Ziadi and Goerschwin Fey.
    Towards analysing feature locations through testing traces with BUT4Reuse.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), pages 10-15, 2015.


  • Heinz Riener and Rüdiger Ehlers and Goerschwin Fey.
    Path-Based Program Repair.
    International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS, pages 22-32, 2015.


  • Heinz Riener and Michael Kirkedal Thomsen and Goerschwin Fey.
    Execution Tracing of C Code for Formal Analysis (Extended Abstract).
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 160-164, 2015.


  • Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz.
    Conservatively Analyzing Transient Faults.
    IEEE Annual Symposium on VLSI (ISVLSI), pages 50-55, 2015.


  • Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz.
    Analyzing an SET at Gate Level using a Conservative Approach.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2015.


  • Niels Thole and Heinz Riener and Fey, Goerschwin.
    Equivalence Checking on System Level using A Priori Knowledge.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 177-182, 2015.


  • Trond Ytterdal and Snorre Aunet and General Chairs and Bjørn B. Larsen and Görschwin Fey (editors).
    22nd European conference on circuit theory and design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015.
    European Conference on Circuit Theory and Design (ECCTD), 2015.


2014

  • Kai Borchers and Goerschwin Fey and Daniel Luedtke.
    Automatic Performance Tracking of a SpaceWire Network.
    International SpaceWire Conference, 2014.


  • Mehdi Dehbashi and Goerschwin Fey.
    Debug Automation for Synchronization Bugs at RTL.
    VLSI Design Conference, pages 44-49, 2014.
    [doi: 10.1109/VLSID.2014.15]

  • Mehdi Dehbashi and Goerschwin Fey.
    Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs.
    Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP), pages 400-404, 2014.
    [doi: 10.1109/PDP.2014.72]

  • Mehdi Dehbashi and Goerschwin Fey.
    SAT-Based Speedpath Debugging Using Waveforms.
    IEEE European Test Symposium (ETS), pages 63-68, 2014.


  • Mehdi Dehbashi and Goerschwin Fey.
    Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2014.


  • Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers).
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe).
    2014.


  • Stephan Eggersglüß and Goerschwin Fey and Ilia Polian.
    Test digitaler Schaltkreise.
    2014.


  • Goerschwin Fey.
    Command and Data Handling Infrastructure for Space Systems (Invited Talk).
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), 2014.


  • Alexander Finder and André Sülflow and Goerschwin Fey.
    Latency Analysis for Sequential Circuits.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 643-647, 2014.
    [doi: 10.1109/TCAD.2013.2292501]

  • Daniel Lüdtke and Karsten Westerdorff and Kai Stohlmann and Anko Börner and Olaf Maibaum and Ting Peng and Benjamin Weps and Goerschwin Fey and Andreas Gerndt.
    OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft.
    IEEE Aerospace Conference (AEROCONF), 2014.


  • Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey.
    Mutation based Feature Localization.
    International Workshop on Microprocessor Test and Verification (MTV), pages 49-54, 2014.


  • Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey.
    Mutation based Feature Localization.
    Workshop on Design Automation for Understanding Hardware Designs (DUHDe), 2014.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    A Simulation Based Approach for Automated Feature Localization.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 1886-1899, 2014.
    [doi: 10.1109/TCAD.2014.2360462]

  • Jan Malburg and Niklas Krafczyk and Goerschwin Fey.
    Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2014.


  • Heinz Riener and Oliver Keszocze and Rolf Drechsler and Goerschwin Fey.
    A Logic for Cardinality Constraints (Extended Abstract).
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 217-220, 2014.


  • Heinz Riener and Mathias Soeken and Clemens Werther and Goerschwin Fey and Rolf Drechsler.
    metaSMT: A Unified Interface to SMT-LIB2.
    Forum on Specification and Design Languages (FDL), 2014.


  • Niels Thole and Goerschwin Fey.
    Equivalence Checking on System Level using Stepwise Induction.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 197-200, 2014.


  • Carl Johann Treudler and Jan-Carsten Schröder and Fabian Greif and Kai Stohlmann and Gökçe Aydos and Goerschwin Fey.
    Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions.
    Data Systems In Aerospace (DASIA), 2014.


2013

  • Rob Aitken and Goerschwin Fey and Zbigniew T. Kalbarczyk and Frank Reichenbach and Matteo Sonza Reorda.
    Reliability Analysis Reloaded: How Will We Survive?.
    Design, Automation and Test in Europe (DATE), pages 358-367, 2013.


  • Mehdi Dehbashi and Goerschwin Fey.
    Debug Automation for Logic Circuits Under Timing Variations.
    In IEEE Design and Test of Computers (DT), pages 60-69, 2013.
    [doi: 10.1109/MDAT.2013.2266393]

  • Mehdi Dehbashi and Goerschwin Fey.
    Efficient Automated Speedpath Debugging.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 48-53, 2013.


  • Mehdi Dehbashi and Goerschwin Fey.
    Towards Debug Automation for Timing Bugs at RTL.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2013.


  • Mehdi Dehbashi and André Sülflow and Goerschwin Fey.
    Automated Design Debugging in a Testbench-Based Verification Environment.
    In Microprocessors and Microsystems (MICPRO), pages 206-217, 2013.


  • Goerschwin Fey and Matteo Sonza Reorda (Organizers).
    Reliability Analysis Reloaded: How Will We Survive? (Embedded Tutorial).
    Design, Automation and Test in Europe (DATE), 2013.


  • Alexander Finder and Jan-Philipp Witte and Goerschwin Fey.
    Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 60-65, 2013.


  • Daniel Grosse and Goerschwin Fey and Rolf Drechsler.
    Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis.
    In Electronic Communications of the EASST, pages 13 pages, 2013.
    [doi: 10.14279/tuj.eceasst.62.860.854]

  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Tuning Dynamic Data Flow Analysis to Support Design Understanding.
    Design, Automation and Test in Europe (DATE), pages 1179-1184, 2013.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 59-66, 2013.


  • Heinz Riener and Goerschwin Fey.
    Yet a Better Error Explanation Algorithm (Extended Abstract).
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 193-194, 2013.


  • Heinz Riener and Stefan Frehse and Goerschwin Fey.
    Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis.
    Design, Automation and Test in Europe (DATE), pages 939-942, 2013.


  • Luká? Sekanina and Görschwin Fey and Jaan Raik and Snorre Aunet and Richard Ruzicka (editors).
    16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2013.


2012

  • Roderick Bloem and Rolf Drechsler and Goerschwin Fey and Alexander Finder and Georg Hofferek and Robert Könighofer and Jaan Raik and Urmas Repinski and André Sülflow.
    FoREnSiC - An Automatic Debugging Environment for C Programs.
    IBM Haifa Verification Conference (HVC), pages 260-265, 2012.


  • Mehdi Dehbashi and Goerschwin Fey.
    Automated Debugging from Pre-Silicon to Post-Silicon.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 324-329, 2012.


  • Mehdi Dehbashi and Goerschwin Fey.
    Automated Post-Silicon Debugging of Failing Speedpaths.
    Asian Test Symposium (ATS), pages 13-18, 2012.


  • Mehdi Dehbashi and Goerschwin Fey.
    Application of Timing Variation Modeling to Speedpath Diagnosis.
    System, Software, SoC and Silcon Debug Conference (S4D), pages 34-37, 2012.


  • Mehdi Dehbashi and Goerschwin Fey.
    Automated Debugging from Pre-Silicon to Post-Silicon.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2012.


  • Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan.
    Functional Analysis of Circuits Under Timing Variations.
    IEEE European Test Symposium (ETS), pages 177, 2012.


  • Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan.
    Functional Analysis of Circuits Under Timing Variations.
    edaWorkshop, pages 45-50, 2012.


  • Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan.
    On Modeling and Evaluation of Logic Circuits Under Timing Variations.
    EUROMICRO Symposium on Digital System Design (DSD), pages 431-436, 2012.


  • Goerschwin Fey.
    Assessing System Vulnerability using Formal Verification Techniques.
    Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS) - Revised Selected Papers, pages 47-56, 2012.


  • Finder, Alexander and Fey, Görschwin.
    Evaluating Debugging Algorithms from a Qualitative Perspective.
    System Specification and Design Languages - Selected Contributions from FDL 2010, pages 21-36, 2012.


  • Stefan Frehse and Goerschwin Fey and Eli Arbel and Karen Yorav and Rolf Drechsler.
    Complete and Effective Robustness Checking by Means of Interpolation.
    Formal Methods in Computer-Aided Design (FMCAD), pages 82-90, 2012.


  • Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (editors).
    Verifying Reliability (Dagstuhl Seminar 12341).
    In Dagstuhl Reports, pages 57-73, 2012.
    [doi: http://dx.doi.org/10.4230/DagRep.2.8.57]

  • Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (Organizers).
    Verifying Reliability (Dagstuhl Seminar 12341).
    In Dagstuhl Reports, 2012.


  • Stefan Frehse and Heinz Riener and Goerschwin Fey.
    Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 90-96, 2012.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Automated Feature Localization for Hardware Designs using Coverage Metrics.
    Design Automation Conference (DAC), pages 941-946, 2012.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Automated Feature Localization for Hardware Designs using Coverage Metrics.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012.


  • Jaan Raik (Organizer).
    Panel: Can RTL test techniques be applied to software?.
    2012.


  • Heinz Riener and Goerschwin Fey.
    Model-Based Diagnosis versus Error Explanation.
    ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE), pages 43-52, 2012.


  • Heinz Riener and Goerschwin Fey.
    FAUST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.
    International SPIN Workshop on Model Checking of Software (SPIN), pages 234-240, 2012.


  • Heinz Riener and Goerschwin Fey.
    Model-Based Diagnosis versus Error Explanation.
    International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES), 2012.


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