2021

  • 21-999 BKF:2021 ETS (2021). Designing Recurrent Neural Networks for Monitoring Embedded Devices. IEEE European Test Symposium (ETS)

  • 21-999 BKF:2021b MOCAST (2021). Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference. International Conference on Circuits and Systems Technologies (MOCAST)

  • 21-999 GBE+:2021 ATS (2021). Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining. Asian Test Symposium (ATS)

  • 21-999 MBE+:2021 DSD_EUROMICRO (2021). Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems. EUROMICRO Symposium on Digital System Design (DSD)

  • 21-999 PMF:2021 DSD_EUROMICRO (2021). Metrics for the Evaluation of Approximate Sequential Streaming Circuits. EUROMICRO Symposium on Digital System Design (DSD)

  • 21-999 PSF:2021b MBMV (2021). Extended Abstract: Viability of Decision Trees for Learning Models of Systems. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)

  • 21-999 PSH+:2021 LEAC (2021). Automata Learning for Automated Test Generation of Real Time Localization Systems. Workshop on Machine Learning in Control (Learning in Control, LEAC)

  • 21-999 SPBF:2021 SE4ICPS (2021). Learning Models of Cyber-Physical Systems using Automata Learning. Software Engineering for Industrial Cyber-Physical Systems (SE4ICPS)

  • Fin Hendrik Bahnsen and Goerschwin Fey (2021). YAPS - Your Open Examination System for Activating and emPowering Students. In Editor (Eds.) IEEE International Conference on Computer Science and Education (ICCSE) Publisher: Addresse Seiten [Abstract]

2020

  • 20-999 BF:2020 TUZ (2020). Emulation of Neural Networks under HW Faults. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

  • 20-999 MRF:2020 DSD (2020). Revisiting Explicit Enumeration for Exact Synthesis. In Proceedings of Euromicro Conference on Digital System Design (DSD) Portorož / Slovenia

2019

  • 19-999 BF:2019 DSD_EUROMICRO (2019). Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. EUROMICRO Symposium on Digital System Design (DSD) 485-491

  • 19-999 BF:2019b MBMV (2019). Approximation of Neural Networks for Verification. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)

  • 19-999 BF:2019c TUZ (2019). Neural Networks for Monitoring Embedded Devices. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

  • 19-999 BFG+:2019 FMSD (2019). Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. Formal Methods in System Design (FMSD).

  • 19-999 FD:2019b MBMV (2019). Self-Explaining Digital Systems - Some Technical Steps. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)

  • 19-999 FD:2019c {ADVANCED BOOLEAN TECHNIQUES -- SELECTED PAPERS FROM THE 13TH INTERNATIONAL WORKSHOP ON BOOLEAN PROBLEMS} (2019). Self-Explaining Digital Systems: Technical View, Implementation Aspects, and Completeness. In Rolf Drechsler and Mathias Soeken (Eds.) Advanced Boolean Techniques - Selected Papers from the 13th International Workshop on Boolean Problems Springer:

  • 19-999 FG:2019 ETS (2019). Symbolic Circuit Analysis under an Arc Based Timing Model. IEEE European Test Symposium (ETS)

  • 19-999 GMD+:2019 VLSISOC (2019). Engineering of an Effective Automatic Dynamic Assertion Mining Platform. IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC)

  • 19-999 GMD+:2019b DUHDE (2019). Engineering of an Effective Automatic Assertion-based Verification Platform. Workshop on Design Automation for Understanding Hardware Designs (DUHDe)

  • 19-999 MF:2019 FDL (2019). Syntax-Guided Enumeration of Temporal Properties. In Proceedings of Forum on Specification and Design Languages (FDL) Southampton / United Kingdom

  • 19-999 MRF:2019 DUHDE (2019). Complete Specification Mining. In Proceedings of Workshop on Design Automation for Understanding Hardware Designs (DUHDE) Florence / Italy

2018

  • 18-999 FGJMRR:2018 VLSI-SoC (2018). Design Understanding: From Logic to Specification. In Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) Verona / Italy

  • 18-999 JTH+:2018 DDECS (2018). Software-Level TMR Approach for On-Board Data Processing in Space Applications. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

  • 18-999 MRF:2018 IWLS (2018). Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems. In Proceedings of International Workshop on Logic & Synthesis (IWLS) San Francisco / USA

  • 18-999 MRF:2018b ISMVL (2018). Mining Latency Guarantees for RTL Designs. IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)

  • 18-999 TF:2018 DDECS (2018). Augmenting All Solutions SAT Solving for Circuits with Structural Information. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

2017

  • 17-999 AF:2017 MICPRO (2017). Empirical Results on Parity-based Soft Error Detection with Software-based Retry. Microprocessors and Microsystems (MICPRO). 62-68

  • 17-999 ASVF:2017 JETTA (2017). A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. Journal of Electronic Testing: Theory and Applications (JETTA). 53-64

  • 17-999 FF:2017 DDECS (2017). Mapping Abstract and Concrete Hardware Models for Design Understanding. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

  • 17-999 FMF+:2017 ISVLSI (2017). Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. IEEE Annual Symposium on VLSI (ISVLSI)

  • 17-999 MFF:2017 ASPDAC (2017). Property Mining using Dynamic Dependency Graphs. ASP Design Automation Conference (ASPDAC) 244-250

  • 17-999 MRF:2017 DUHDE (2017). Mining Latency Guarantees for RT-level Designs. Workshop on Design Automation for Understanding Hardware Designs (DUHDe)

  • 17-999 MSF:2017 AEROCONF (2017). Adaptive Compression Schemes for Housekeeping Data. IEEE Aerospace Conference (AEROCONF)

  • 17-999 REF:2017 ASPDAC (2017). CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification. ASP Design Automation Conference (ASPDAC) 251-256

  • 17-999 REF:2017b MBMV (2017). Counterexample-Guided EF Synthesis of Boolean Functions. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)

  • 17-999 RF:2017b DUHDE (2017). Computing Exact Fault Candidates Incrementally. Workshop on Design Automation for Understanding Hardware Designs (DUHDe)

  • 17-999 RKFB:2016 ARCH (2017). SMT-Based CPS Parameter Synthesis. Applied Verification for Continuous and Hybrid Systems (ARCH) 126-133

  • 17-999 SGF:2017 IOLTS (2017). Temporal Redundancy Latch-based Architecture for Soft Error Mitigation. IEEE International On-Line Testing Symposium (IOLTS) 240-243

  • 17-999 SGF:2017b IOLTS (2017). Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.

  • 17-999 TF:2017 TUZ (2017). Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

2016

  • 16-999 AAB+:2016 FDL (2016). Designing Reliable Cyber-Physical Systems. Forum on Specification and Design Languages (FDL)

  • 16-999 MFF:2016b IVSW (2016). Generating Good Properties from a Small Number of Use Cases. International Verification and Security Workshop (IVSW)

  • 16-999 TAF:2016c TUZ (2016). A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

  • 16-999 TAF:2016b ISVLSI (2016). A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. IEEE Annual Symposium on VLSI (ISVLSI) 278-283

  • 16-999 TAF:2016 ETS (2016). A Hybrid Algorithm to Conservatively Check the Robustness of Circuits (extended abstract). IEEE European Test Symposium (ETS) 2

  • 16-999 RHF+:2016 STTT (2016). metaSMT: Focus On Your Application And Not On Solver Integration. International Journal on Software Tools for Technology Transfer (STTT). 1-17

  • 16-999 RF:2016c IVSW (2016). Counterexample-Guided Diagnosis. International Verification and Security Workshop (IVSW)

  • 16-999 RF:2016 ICCAD (2016). Exact Diagnosis using Boolean Satisfiability. IEEE/ACM Int'l Conf. on CAD (ICCAD) 53:1-53:8

  • 16-999 MSFD:2016 TTC (2016). On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms. ESA International Tracking, Telemetry and Command Systems for Space Applications (TTC)

  • 16-999 MFF:2016 MICPRO (2016). Debugging hardware designs using dynamic dependency graphs. Microprocessors and Microsystems (MICPRO). 347-359

  • 16-999 AF:2016b DDECS (2016). Exploiting Error Detection Latency for Parity-based Soft Error Detection. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

  • 16-999 KRF:2016 VLSISOC (2016). WCET Overapproximation for Software in the Context of a Cyber-Physical System. IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC)

  • 16-999 HRFS:2016b ICCAD (2016). Multilevel Design Understanding: From Specification to Logic (Special Session).

  • 16-999 FR:2016 FDL (2016). Designing Reliable Cyber-Physical Systems.

  • 16-999 FHRS:2016 ICCAD (2016). Multilevel Design Understanding: From Specification to Logic. IEEE/ACM Int'l Conf. on CAD (ICCAD)

  • 16-999 FF:2016 DUHDE (2016). Matching Abstract and Concrete Hardware Models for Design Understanding. Workshop on Design Automation for Understanding Hardware Designs (DUHDe)

  • 16-999 ASVF:2016 LATS (2016). Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables. IEEE Latin-American Test Symposium (LATS) 14-19

  • 16-999 ASV+:2016 IOLTS (2016). On the robustness of compression algorithms for space applications. IEEE International On-Line Testing Symposium (IOLTS)

  • 16-999 TRF:2016 FDL (2016). Equivalence Checking on ESL Utilizing A Priori Knowledge. Forum on Specification and Design Languages (FDL)

2015

  • 15-999 AF:2015 NORCAS (2015). Empirical Results on Parity-based Soft Error Detection with Software-based Retry. IEEE Nordic Circuits and Systems Conference (NORCAS)

  • 15-999 DF:2014e (2015). Debug Automation from Pre-Silicon to Post-Silicon.

  • 15-999 DF:2015 MICPRO (2015). Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocessors and Microsystems (MICPRO). 157-166

  • 15-999 EF:2015 (2015). Workshop on Design Automation for Understanding Hardware Designs (DUHDe).

  • 15-999 FSF:2015 ATS (2015). Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation. Asian Test Symposium (ATS) 145-150

  • 15-999 MMZF:2015 DUHDE (2015). Towards analysing feature locations through testing traces with BUT4Reuse. Workshop on Design Automation for Understanding Hardware Designs (DUHDe) 10-15

  • 15-999 REF:2015 FESCA (2015). Path-Based Program Repair. International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS 22-32

  • 15-999 RKF:2015 MBMV (2015). Execution Tracing of C Code for Formal Analysis (Extended Abstract). ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 160-164

  • 15-999 TFG:2015 ISVLSI (2015). Conservatively Analyzing Transient Faults. IEEE Annual Symposium on VLSI (ISVLSI) 50-55

  • 15-999 TFG:2015b TUZ (2015). Analyzing an SET at Gate Level using a Conservative Approach. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

  • 15-999 TRF:2015 DDECS (2015). Equivalence Checking on System Level using A Priori Knowledge. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 177-182

  • 15-999 YA+:2015 ECCTD (2015). 22nd European conference on circuit theory and design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015.

2014

  • 14-999 BFL:2014 SPW (2014). Automatic Performance Tracking of a SpaceWire Network. International SpaceWire Conference

  • 14-999 MEF:2014 MTV (2014). Mutation based Feature Localization. International Workshop on Microprocessor Test and Verification (MTV) 49-54

  • 14-999 TF:2014 MBMV (2014). Equivalence Checking on System Level using Stepwise Induction. ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 197-200

  • 14-999 RSW+:2014 FDL (2014). metaSMT: A Unified Interface to SMT-LIB2. Forum on Specification and Design Languages (FDL)

  • 14-999 RKDF:2014 MBMV (2014). A Logic for Cardinality Constraints (Extended Abstract). ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 217-220

  • 14-999 MKF:2014 DDECS (2014). Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

  • 14-999 MFF:2014 TCAD (2014). A Simulation Based Approach for Automated Feature Localization. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 1886-1899

  • 14-999 MEF:2014b DUHDE (2014). Mutation based Feature Localization. Workshop on Design Automation for Understanding Hardware Designs (DUHDe)

  • 14-999 LWS+:2014 AEROCONF (2014). OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft. IEEE Aerospace Conference (AEROCONF)

  • 14-999 DF:2014b VLSIDC (2014). Debug Automation for Synchronization Bugs at RTL. VLSI Design Conference 44-49

  • 14-999 FSF:2014 TCAD (2014). Latency Analysis for Sequential Circuits. IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD). 643-647

  • 14-999 Fey:2014 ISMVL (2014). Command and Data Handling Infrastructure for Space Systems (Invited Talk). IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)

  • 14-999 EFP:2014 (2014). Test digitaler Schaltkreise.

  • 14-999 EF:2014 (2014). Workshop on Design Automation for Understanding Hardware Designs (DUHDe).

  • 14-999 DF:2014f TUZ (2014). Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

  • 14-999 DF:2014d ETS (2014). SAT-Based Speedpath Debugging Using Waveforms. IEEE European Test Symposium (ETS) 63-68

  • 14-999 DF:2014c PDP (2014). Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP) 400-404

  • 14-999 TSG+:2014 DASIA (2014). Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions. Data Systems In Aerospace (DASIA)

2013

  • 13-999 AFK+:2013 DATE (2013). Reliability Analysis Reloaded: How Will We Survive?. Design, Automation and Test in Europe (DATE) 358-367

  • 13-999 DF:2013 DT (2013). Debug Automation for Logic Circuits Under Timing Variations. IEEE Design and Test of Computers (DT). 60-69

  • 13-999 DF:2013c DDECS (2013). Efficient Automated Speedpath Debugging. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 48-53

  • 13-999 DF:2013e TUZ (2013). Towards Debug Automation for Timing Bugs at RTL. GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)

  • 13-999 DSF:2013 MICPRO (2013). Automated Design Debugging in a Testbench-Based Verification Environment. Microprocessors and Microsystems (MICPRO). 206-217

  • 13-999 FS:2013 DATE (2013). Reliability Analysis Reloaded: How Will We Survive? (Embedded Tutorial).

  • 13-999 FWF:2013 DDECS (2013). Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications. IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 60-65

  • 13-999 GFD:2013 ECEASST (2013). Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electronic Communications of the EASST. 13 pages

  • 13-999 MFF:2013 DATE (2013). Tuning Dynamic Data Flow Analysis to Support Design Understanding. Design, Automation and Test in Europe (DATE) 1179-1184

  • 13-999 MFF:2013b ZUE (2013). Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE) 59-66

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