@article{JF25,
Author = {Shashank Jadhav and Heiko Falk},
Title = {Compiler-level DMA-aware multi-objective dynamic SPM allocation.},
Journal = {<em>The International Journal of Time-Critical Computing Systems (Real-Time Systems)</em>.},
Year = {(2025).},
Month = {April},
Note = {sjadhav, hfalk, memopt, ESD, WCC},
Publisher = {Springer:},
Isbn = {10.1007/s11241-025-09436-w},
Howpublished = {25-95 JF24 RTS},
Doi = {10.1007/s11241-025-09436-w},
Abstract = {Real-time embedded systems need to meet timing and energy constraints to avoid potential disasters. Compiler-level ScratchPad Memory (SPM) allocation can be used to optimize a program's Worst-Case Execution Time (WCET) and energy consumption. However, static allocation is limited by SPM size constraints. Dynamic SPM allocation resolves this by allocating code to SPM during runtime, but copying code using the CPU increases WCET and energy consumption. To address this, we integrate a Direct Memory Access (DMA) model and DMA analysis at the compiler level and propose a single-objective DMA Call Placement Optimization (DCPO). In this paper, we consider functions and loops as dynamic allocation candidates. DCPO finds appropriate places within the code to place DMA transfer calls such that the DMA controller and the CPU run parallelly—minimizing the total execution time required by the DMA controller for dynamic allocation of functions and loops during runtime. Additionally, we propose a compiler-level DMA-aware multi-objective dynamic SPM allocation that uses DCPO and simultaneously minimizes WCET and energy objectives, yielding Pareto optimal solutions. Comparative evaluations demonstrate the superiority of our approach over state-of-the-art multi- and single-objective optimizations.}
}

@inproceedings{GETF:2024,
Author = {Arne Grünhagen and Annika Eichler and Marina Tropmann-Frick and Goerschwin Fey},
Title = {Data-Driven Fault Localization in Cyber-Physical Systems Using Dependency Graphs and Anomaly Detection.},
Year = {(2024).},
Note = {gfey, CE},
Howpublished = {24-99917 GETF:2024 EJC},
Booktitle = {<em>International Conference on Information Modelling and Knowledge Bases (EJC)</em>}
}

@incollection{KPF:2024,
Author = {Arne Krumnow and Swantje Plambeck and Goerschwin Fey},
Title = {Using Forest Structures for Passive Automata Learning.},
Year = {(2024).},
Note = {gfey, splambeck, CE},
Editor = {In Oliver Niggemann et al. (editors) (Eds.)},
Publisher = {Springer International Publishing:},
Isbn = {https://doi.org/10.1007/978-3-031-47062-2_7},
Howpublished = {24-99916 KPF:2024}
}

@inproceedings{SMF:2024,
Author = {Lutz Schammer and Gianluca Martino and Goerschwin Fey},
Title = {Tag-based Hardware Information Flow Tracking.},
Year = {(2024).},
Note = {gfey, lschammer, gmartino, CE},
Howpublished = {24-99914 SMF:2024 TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{SPF:2024,
Author = {Maximilian Schmidt and Swantje Plambeck and Görschwin Fey},
Title = {Towards Robustness Evaluation of Models for Cyber-Physical Systems.},
Year = {(2024).},
Note = {gfey, splambeck, CE},
Howpublished = {24-99913 SPF:2024 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{SBHF:2024,
Author = {Swantje Plambeck and Aaron Bracht and Nemanja Hranisavljevic and Goerschwin Fey},
Title = {FaMoS - Fast Model Learning for Hybrid Cyber-Physical Systems using Decision Trees.},
Year = {(2024).},
Note = {gfey, splambeck, CE},
Howpublished = {24-99915 SBHF:2024 HSCC},
Booktitle = {<em>ACM International Conference on Hybrid Systems: Computation and Control (HSCC)</em>}
}

@inproceedings{FF24,
Author = {Thilo Fischer and Heiko Falk},
Title = {Shared Cache Analysis under Preemptive Scheduling.},
Year = {(2024).},
Month = {March},
Note = {tfischer, hfalk, ESD, WCC},
Howpublished = {24-95 FF24 DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Abstract = {When sharing a cache between multiple cores, the inter-core interference has to be considered in the worst-case execution time (WCET) analysis. Current interference models are overly pessimistic or not applicable to preemptively scheduled systems. We propose a novel technique to model interference in a preemptive system to classify accesses as cache hits or potential misses. We account for inter-core interference by considering the potential execution scenarios on the interfering core and find the worst-case interference pattern. The resulting access classifications are then used to compute the cache-related preemption delay. Our evaluation shows that the proposed analysis significantly increases the cache hit classifications, reduces WCET on average by up to 11.7%, and reduces worst-case response times on average by up to 15.4% compared to the existing classification technique.}
}

@article{FF24,
Author = {Thilo Fischer and Heiko Falk},
Title = {Towards Analysing Cache-Related Preemption Delay in Non-Inclusive Cache Hierarchies.},
Journal = {<em>ACM Transactions on Embedded Computing Systems (TECS)</em>.},
Year = {(2024).},
Month = {September},
Note = {tfischer, hfalk, ESD, WCC},
Publisher = {ACM:},
Isbn = {10.1145/3695768},
Howpublished = {24-90 FF24 TECS},
Abstract = {The impact of preemptions has to be considered when determining the schedulability of a task set in a preemptively scheduled system. In particular, the contents of caches can be disturbed by a preemption, thus creating context-switching costs. These context-switching costs occur when a preempted task needs to reload data from memory after a preemption. The additional delay created by this effect is termed cache-related preemption delay (CRPD). The analysis of CRPD has been extensively studied for single-level caches in the past. However, for two-level caches, the analysis of CRPD is still an emerging area of research. In contrast to a single-level cache, which is only affected by direct preemption effects, the second-level cache in a two-level hierarchy can be subject to indirect interference after a preemption. Accesses that could be served from the L1 cache in the absence of preemptions, may be forwarded to the L2 cache, as the relevant data was evicted by a preemption. These accesses create the indirect interference in the L2 cache and can cause further evictions. Recently, a CRPD analysis for two-level non-inclusive cache hierarchies was proposed. In this paper, we show that this state-of-the-art analysis is unsafe as it potentially underestimates the CRPD. Furthermore, we show that the analysis is pessimistic and can overestimate the indirect preemption effects. To address these issues, we propose a novel analysis approach for the CRPD in a two-level non-inclusive cache hierarchy. We prove the correctness of the presented approach based on the set of feasible program execution traces. We implemented the presented approach in a worst-case execution time (WCET) analysis tool and compared the performance to existing analysis methods. Our evaluation shows that the presented analysis increases task set schedulability by up to 14 percentage points compared to the state-of-the-art analysis.}
}

@article{FF24b,
Author = {Thilo Fischer and Heiko Falk},
Title = {Timing-aware analysis of shared cache interference for non-preemptive scheduling.},
Journal = {<em>The International Journal of Time-Critical Computing Systems (Real-Time Systems)</em>.},
Year = {(2024).},
Month = {September},
Note = {tfischer, hfalk, ESD, WCC},
Publisher = {Springer:},
Isbn = {10.1007/s11241-024-09430-8},
Howpublished = {24-85 FF24b RTS},
Abstract = {In multi-core architectures, the last-level cache (LLC) is often shared between cores. Sharing the LLC leads to inter-core interference, which impacts system performance and predictability. This means that tasks running in parallel on different cores may experience additional LLC misses as they compete for cache space. To compute a task’s worst-case execution time (WCET), a safe bound on the inter-core cache interference has to be determined. We propose an interference analysis for set-associative shared least-recently-used caches. The analysis leverages timing information to establish tight bounds on the worst-case interference and classifies individual accesses as either cache hits or potential cache misses. We evaluated the analysis performance for systems containing 2 and 4 cores using shared caches up to 64 KB. The evaluation shows an average WCET reduction of up to 23.3% for dual-core systems and 8.5% for quad-core systems.}
}

@inproceedings{AGF:2023,
Author = {Abdelaziz, Khaled Galal Abdelwahab and Görgen, Ralph and Fey, Goerschwin},
Title = {FINaL: Driving High-Level Fault Injection Campaigns with Natural Language.},
Year = {(2023).},
Note = {gfey, CE},
Howpublished = {23-9992 AGF:2023 ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@inproceedings{ASMF:2023,
Author = {Ahmad Al-Zoubi and Benedikt Schaible and Gianluca Martino and Goerschwin Fey},
Title = {Latency-optimized Hardware Acceleration of Multilayer Perceptron Inference.},
Year = {(2023).},
Note = {gfey, gmartino, alzoubi, CE},
Isbn = {10.1109/DSD60849.2023.00042},
Howpublished = {23-9999 ASMF:2023 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@incollection{AF:2023,
Author = {Al-Zoubi, Ahmad and Fey, Goerschwin},
Title = {Low-Latency Real-Time Inference for Multilayer Perceptrons on FPGAs.},
Year = {(2023).},
Pages = {123-133},
Note = {gfey, alzoubi, CE},
Editor = {In Drechsler, Rolf and Huhn, Sebastian (editors) (Eds.)},
Publisher = {Springer International Publishing:},
Isbn = {10.1007/978-3-031-28916-3_9},
Howpublished = {23-99912 AF:2023}
}

@inproceedings{GETF:2023,
Author = {Arne Grünhagen and Annika Eichler and Marina Tropmann-Frick and Goerschwin Fey},
Title = {Condition Monitoring and Fault Detection of a Laser Oscillator Feedback System.},
Year = {(2023).},
Note = {gfey, CE},
Howpublished = {23-9996 GETF:2023 EJC},
Booktitle = {<em>International Conference on Information Modelling and Knowledge Bases (EJC)</em>}
}

@inproceedings{GSE+:2023,
Author = {Arne Grünhagen and Maximilian Schütte and Annika Eichler and Marina Tropmann-Frick and Goerschwin Fey},
Title = {Enhancing Data Acquisition and Fault Analysis for Large-Scale Facilities: A Case Study on the Laser-Based Synchronization System at the European X-Ray Free-Electron Laser [Work in progress].},
Year = {(2023).},
Note = {gfey, CE},
Howpublished = {23-99911 GSE+:2023 LWDA},
Booktitle = {<em>GI Workshop on Learning, Knowledge, Data, Analytics (LWDA)</em>}
}

@inproceedings{RBE+23,
Author = {Benjamin Rouxel, Christopher Brown, Emad Ebeid, Kerstin Eder, Heiko Falk, Clemens Grelck, Jesper Holst, Shashank Jadhav, Yoann Marquer, Marcos Martinez De Alejandro, Kris Nikov, Ali Sahafi, Ulrik Schultz, Adam Seewald, Vangelis Vassalos, Simon Wegener and Olivier Zendra},
Title = {The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems.},
Year = {(2023).},
Month = {April},
Note = {sjadhav, hfalk, teamplay, ESD, WCC},
Howpublished = {23-90 RBE+23 DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Abstract = {Non-functional properties, such as energy, time, and security (ETS) are becoming increasingly important in Cyber- Physical Systems (CPS) programming. This article describes TeamPlay, a research project funded under the EU Horizon 2020 programme between January 2018 and June 2021. TeamPlay aimed to provide the system designer with a toolchain for developing embedded applications where ETS properties are first-class citizens, allowing the developer to reflect directly on energy, time and security properties at the source code level. In this paper we give an overview of the TeamPlay methodology, introduce the challenges and solutions of our approach and summarise the results achieved. Overall, applying our TeamPlay methodology led to an improvement of up to 18% performance and 52% energy usage over traditional approaches.}
}

@inproceedings{BF:2023,
Author = {Bernhard Johannes Berger and Goerschwin Fey},
Title = {Towards: Threat Modeling in System Design.},
Year = {(2023).},
Note = {gfey, CE},
Howpublished = {23-9993 BF:2023 TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{BBF:2023,
Author = {Fin Hendrik Bahnsen and Bernhard J. Berger and Goerschwin Fey},
Title = {GLRP: Guided by Layer-wise Relevance Propagation - Selecting Crucial Neurons in Artificial Neural Networks.},
Year = {(2023).},
Note = {gfey, fbahnsen, CE},
Isbn = {10.1109/MOCAST57943.2023.10176688},
Howpublished = {23-9997 BBF:2023 MOCAST},
Booktitle = {<em>International Conference on Circuits and Systems Technologies (MOCAST)</em>}
}

@inproceedings{BBF:2023b,
Author = {Fin Hendrik Bahnsen and Bernhard Johannes Berger and Goerschwin Fey},
Title = {DoCNeL: Detection of Crucial Neurons Guided by Layer-wise Relevance Propagation.},
Year = {(2023).},
Note = {gfey, fbahnsen, CE},
Howpublished = {23-9994 BBF:2023b TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{GTEF:2023b,
Author = {Grünhagen, Arne and Tropmann-Frick, Marina and Eichler, Annika and Fey, Goerschwin},
Title = {Predictive Maintenance for the Optical Synchronization System of the European XFEL: A Systematic Literature Survey.},
Year = {(2023).},
Note = {gfey, CE},
Howpublished = {23-9995 GTEF:2023b DE4DS},
Booktitle = {<em>Data Engineering for Data Science (DE4DS)</em>}
}

@inproceedings{AHFL:2023,
Author = {Hany Abdelmaksoud and Zain A. H. Hammadeh and Goerschwin Fey and Daniel Lüdtke},
Title = {DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation.},
Year = {(2023).},
Note = {gfey, CE},
Howpublished = {23-9991 AHFL:2023 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{MF23,
Author = {Kateryna Muts and Heiko Falk},
Title = {Clustering Solutions of Multiobjective Function Inlining Problem.},
Year = {(2023).},
Pages = {4:1-2:12},
Month = {July},
Note = {kmuts, hfalk, ESD, WCC},
Address = {Vienna / Austria},
Isbn = {10.4230/OASIcs.WCET.2023.4},
Howpublished = {23-80 MF23 WCET},
Booktitle = {<em>In Proceedings of the 21st International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {Hard real time-systems are often small devices operating on batteries that must react within a given deadline, so they must satisfy their timing, code size, and energy consumption requirements. Since these three objectives contradict each other, compilers for real-time systems go towards multiobjective optimizations which result in sets of trade-off solutions. A system designer can use the solution sets to choose the most suitable system configuration. Evolutionary algorithms can find trade-off solutions but the solution set might be large which complicates the task of the system designer. We propose to divide the solution set into clusters, so the system designer chooses the most suitable cluster and examines a smaller subset in detail. In contrast to other clustering techniques, our method guarantees that the sizes of all clusters are less than a predefined limit. Our method clusters a set by using any existing clustering method, divides clusters with sizes exceeding the predefined size into smaller clusters, and reduces the number of clusters by merging small clusters. The method guarantees that the final clusters satisfy the size constraint. We demonstrate our approach by considering a well-known compiler-based optimization called function inlining. It substitutes function calls by the function bodies which decreases the execution time and energy consumption of a program but increases its code size.}
}

@inproceedings{LKF+:2023,
Author = {Leandro Lanzieri and Peter Kietzmann and Goerschwin Fey and Holger Schlarb and Thomas C. Schmidt},
Title = {Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning.},
Year = {(2023).},
Note = {gfey, CE},
Isbn = {10.1109/DSD60849.2023.00054},
Howpublished = {23-9998 LKF+:2023 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{KPW+:2023,
Author = {Markus Knitt and Swantje Plambeck and Jan Christian Wieck and Julian Kohlisch and Stephan Balduin and Eric MSP Veith and Jakob Schyga and Johannes Hinckeldeyn and Gorschwin Fey and Jochen Kreutzfeldt},
Title = {Towards the Automatic Generation of Models for Prediction, Monitoring, and Testing of Cyber-Physical Systems.},
Year = {(2023).},
Note = {gfey, splambeck, CE},
Howpublished = {23-99910 KPW+:2023 ETFA},
Booktitle = {<em>IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)</em>}
}

@inproceedings{JF23a,
Author = {Shashank Jadhav and Heiko Falk},
Title = {Towards Multi-Objective Dynamic SPM Allocation.},
Year = {(2023).},
Pages = {6:1-6:12},
Month = {July},
Note = {sjadhav, hfalk, memopt, ESD, WCC},
Address = {Vienna / Austria},
Isbn = {10.4230/OASIcs.WCET.2023.6},
Howpublished = {23-70 JF23b WCET},
Booktitle = {<em>In Proceedings of the 21st International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {Most real-time embedded systems are required to fulfill timing constraints while adhering to a limited energy budget. Small ScratchPad Memory (SPM) poses a common hardware constraint on embedded systems. Static SPM allocation techniques are limited by the SPM's stringent size constraint, which is why this paper proposes a Dynamic SPM Allocation (DSA) model at the compiler level for the dynamic allocation of a program to SPM during runtime. To minimize Worst-Case Execution Time (WCET) and energy objectives, we propose a multi-objective DSA-based optimization. Static SPM allocations might inherently use SPM sub-optimally, while all proposed DSA optimizations are only single-objective. Therefore, this paper is the first step towards a DSA that trades WCET and energy objectives simultaneously. Even with extra DSA overheads, our approach provides better quality solutions than the state-of-the-art multi-objective static SPM allocation and ILP-based single-objective DSA approach.}
}

@inproceedings{JF23a,
Author = {Shashank Jadhav and Heiko Falk},
Title = {Efficient and Effective Multi-Objective Optimization for Real-Time Multi-Task Systems.},
Year = {(2023).},
Pages = {5:1-5:12},
Month = {July},
Note = {sjadhav, hfalk, teamplay, ESD, WCC},
Address = {Vienna / Austria},
Isbn = {10.4230/OASIcs.WCET.2023.5},
Howpublished = {23-75 JF23a WCET},
Booktitle = {<em>In Proceedings of the 21st International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {Embedded real-time multi-task systems must often not only comply with timing constraints but also need to meet energy requirements. However, optimizing energy consumption might lead to higher Worst-Case Execution Time (WCET), leading to an un-schedulable system, as frequently executed code can easily differ from timing-critical code. To handle such an impasse in this paper, we formulate a Metaheuristic Algorithm-based Multi-objective Optimization (MAMO) for multi-task real-time systems. But, performing multiple WCET, energy, and schedulability analyses to solve a MAMO poses a bottleneck concerning compilation times. Therefore, we propose two novel approaches - Path-based Constraint Approach (PCA) and Impact-based Constraint Approach (ICA) - to reduce the solution search space size and to cope with this problem. Evaluations showed that PCA and ICA reduced compilation times by 85.31% and 77.31%, on average, over MAMO. For all the task sets, out of all solutions found by ICA-FPA, on average, 88.89% were on the final Pareto front.}
}

@inproceedings{FF23b,
Author = {Thilo Fischer and Heiko Falk},
Title = {Analysis of Shared Cache Interference in Multi-Core Systems using Event-Arrival Curves.},
Year = {(2023).},
Pages = {23-33},
Month = {June},
Note = {tfischer, hfalk, ESD, WCC},
Address = {Dortmund / Germany},
Isbn = {10.1145/3575757.3593643},
Howpublished = {23-85 FF23a RTNS},
Booktitle = {<em>In Proceedings of the 31st International Conference on Real-Time Networks and Systems (RTNS)</em>},
Abstract = {Caches are used to bridge the gap between main memory and the significantly faster processor cores. In multi-core architectures, the last-level cache is often shared between cores. However, sharing a cache causes inter-core interference to emerge. Concurrently running tasks will experience additional cache misses as the competing tasks issue interfering accesses and trigger the eviction of data contained in the shared cache. Thus, to compute a task’s worst-case execution time (WCET), a safe bound on the effects of inter-core cache interference has to be determined. In this paper, we propose a novel analysis approach for shared caches using the least recently used (LRU) replacement policy. The presented analysis leverages timing information to produce tight bounds on the worst-case interference. We describe how inter-core cache interference may be expressed as a function of time using event-arrival curves. Thus, by determining the maximal duration between subsequent accesses to a cache block, it is possible to bound the inter-core interference. This enables us to classify accesses as cache hits or potential misses. We implemented the analysis in a WCET analyzer and evaluated its performance for multi-core systems containing 2, 4, and 8 cores using shared caches from 4 KB to 32 KB. The analysis achieves significant improvements compared to a standard interference analysis with WCET reductions of up to 60%. The average WCET reduction is 9% for dual-core, 15% for quad-core, and 11% for octa-core systems. The analysis runtime overhead ranges from a factor of 4× to 7× compared to the baseline analysis.}
}

@inproceedings{FF23,
Author = {Thilo Fischer and Heiko Falk},
Title = {WCET Analysis of Shared Caches in Multi-Core Architectures using Event-Arrival Curves.},
Year = {(2023).},
Month = {April},
Note = {tfischer, hfalk, ESD, WCC},
Howpublished = {23-95 FF23 DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Abstract = {We propose a novel analysis approach for shared LRU caches to classify accesses as definitive cache hits or potential misses. In this approach inter-core cache interference is modelled as an event stream. Thus, by analyzing the timing between subsequent accesses to a particular cache block, it is possible to bound the inter-core interference. This perspective allows us to classify accesses as cache hits or potential misses using a data-flow analysis. We compare the performance of the presented approach to a partitioning of the shared cache.}
}

@inproceedings{AMB+:2022,
Author = {Ahmad Al-Zoubi and Gianluca Martino and Fin H. Bahnsen and Jun Zhu and Holger Schlarb and Goerschwin Fey},
Title = {CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL.},
Year = {(2022).},
Note = {gfey, fbahnsen, gmartino, alzoubi, CE},
Howpublished = {22-9994 AMB+:2022 SOCC},
Booktitle = {<em>IEEE International System-on-Chip Conference (SOCC)</em>}
}

@inproceedings{AF:2022,
Author = {Ahmad Al-Zoubi and Goerschwin Fey},
Title = {Low Latency Real-Time Inference for Multilayer Perceptrons on FPGAs.},
Year = {(2022).},
Note = {gfey, alzoubi, CE},
Howpublished = {22-9991 AF:2022 IWBP},
Booktitle = {<em>Int'l Workshop on Boolean Problems (IWSBP)</em>}
}

@inproceedings{EPS_infarstructur:2022,
Author = {Estella Francois and Dennis Gallaun and Daniel Sitzmann and Fin Hendrik Bahnsen},
Title = {Das Prüfungssystem YAPS als E-Assessment-Standard an der TUHH.},
Year = {(2022).},
Note = {fbahnsen, CE},
Booktitle = {<em>E-Prüfungs-Symposium (ePS)</em>}
}

@inproceedings{fin:eps2022:workshop,
Author = {Fin Hendrik Bahnsen and Mohamed Sakhri and Jan Dillenberger},
Title = {Kontaktlos Prüfen: Hands on Yet Another Prüfungs System (YAPS).},
Year = {(2022).},
Note = {fbahnsen, CE},
Howpublished = {22-9991 fin:eps2022:workshop},
Booktitle = {<em>E-Prüfungs-Symposium (ePS)</em>}
}

@inproceedings{EPS_infarstructur:2022,
Author = {Fin Hendrik Bahnsen and Mohamed Sakhri and Jan Dillenberger and Daniel Sitzmann},
Title = {Skalierbares E-Assessment mit Docker und Ansible.},
Year = {(2022).},
Note = {fbahnsen, CE},
Booktitle = {<em>E-Prüfungs-Symposium (ePS)</em>}
}

@inproceedings{EPS_infarstructur:2022,
Author = {Fin Hendrik Bahnsen, Mohamed Sakhri, Jan Dillenberger},
Title = {Kontaktlos Prüfen: Hands on Yet Another Prüfungs System (YAPS).},
Year = {(2022).},
Note = {fbahnsen, CE},
Booktitle = {<em>E-Prüfungs-Symposium (ePS)</em>}
}

@inproceedings{MBE+:2022,
Author = {G. Martino and A. Bellandi and A. Eichler and J. Branlard and H. Schlarb and L. Doolittle and S. Aderhold and S. Hoobler and J. Nelson and R. D. Porter and L. Zacarias and A. Benwell and D. Gonnella and A. Ratti and G. Fey},
Title = {Anomaly Detection Based Quench Detection System for CW Operation of SRF Cavities.},
Year = {(2022).},
Note = {gfey, gmartino, CE},
Howpublished = {22-9992 MBE+:2022 LINAC},
Booktitle = {<em>International Linear Accelerator Conference (LINCAC)</em>}
}

@inproceedings{MAB+:2022,
Author = {Gianluca Martino and Ahmad Al Zoubi and Julien Branlard and Holger Schlarb and Goerschwin Fey},
Title = {FPGA-based hardware acceleration of machine learning algorithms for particle accelerators.},
Year = {(2022).},
Note = {gfey, gmartino, CE},
Howpublished = {22-9995 MAB+:2022 LLRF},
Booktitle = {<em>Low-level RF Workshop</em>}
}

@inproceedings{MF:2022,
Author = {Gianluca Martino and Goerschwin Fey},
Title = {Runtime Monitoring of c-LTL Specifications on FPGAs using HLS.},
Year = {(2022).},
Note = {gfey, gmartino, CE},
Howpublished = {22-9999 MF:2022 SMACD},
Booktitle = {<em>International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD)</em>}
}

@inproceedings{FFD:2022,
Author = {Goerschwin Fey and Martin Fränzle and Rolf Drechsler},
Title = {Self-explaination in Systems of Systems.},
Year = {(2022).},
Note = {gfey, CE},
Howpublished = {22-9996 FFD:2022 RE4ES},
Booktitle = {<em>International Workshop on Requirements Engineering for Explainable Systems (RE4ES)</em>}
}

@misc{FaGa22c,
Author = {Heiko Falk and Max Gandyra},
Title = {haRTStone - Benchmark Classification Datasets.},
Year = {(2022).},
Month = {February},
Note = {hfalk, ESD, hartstone},
Address = {Zenodo},
Isbn = {10.5281/zenodo.6064420},
Howpublished = {22-85 FaGa22c Zenodo},
Type = {Open Source Software Artifact,}
}

@misc{FaGa22b,
Author = {Heiko Falk and Max Gandyra},
Title = {haRTStone - Feature Extractor Software.},
Year = {(2022).},
Month = {February},
Note = {hfalk, ESD, hartstone},
Address = {Zenodo},
Isbn = {10.5281/zenodo.6064245},
Howpublished = {22-90 FaGa22b Zenodo},
Type = {Open Source Software Artifact,}
}

@misc{FaGa22a,
Author = {Heiko Falk and Max Gandyra},
Title = {haRTStone - Collection of Existing ANSI-C Benchmarks.},
Year = {(2022).},
Month = {February},
Note = {hfalk, ESD, hartstone},
Address = {Zenodo},
Isbn = {10.5281/zenodo.6062597},
Howpublished = {22-95 FaGa22a Zenodo},
Type = {Open Source Software Artifact,}
}

@inproceedings{SPH+:2022,
Author = {Jakob Schyga and Swantje Plambeck and Johannes Hinckeldeyn and Goerschwin Fey and Jochen Kreutzfeldt},
Title = {Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems.},
Year = {(2022).},
Note = {gfey, splambeck, CE},
Howpublished = {22-9993 SPH+:2022 IPIN},
Booktitle = {<em>Indoor Positioning and Indoor Navigation (IPIN)</em>}
}

@inproceedings{SRKF:2022,
Author = {Lutz Schammer and Jan Runge and Paula Klimach and Goerschwin Fey},
Title = {Design Understanding: Identifying Instruction Pipelines in Hardware Designs.},
Year = {(2022).},
Note = {gfey, lschammer, pklimach, CE},
Howpublished = {22-9998 SRKF:2022 MOCAST},
Booktitle = {<em>International Conference on Circuits and Systems Technologies (MOCAST)</em>}
}

@inproceedings{JaFa22,
Author = {Shashank Jadhav and Heiko Falk},
Title = {Approximating WCET and Energy Consumption for Fast Multi-Objective Memory Allocation.},
Year = {(2022).},
Pages = {162-172},
Month = {June},
Note = {sjadhav, hfalk, ESD, WCC},
Address = {Paris / France},
Isbn = {10.1145/3534879.3534889},
Howpublished = {22-80 JaFa22 RTNS},
Booktitle = {<em>In Proceedings of the 30th International Conference on Real-Time Networks and Systems (RTNS)</em>},
Abstract = {Worst-Case Execution Time (WCET) is the most important design criterion in the domain of hard real-time systems. Most embedded systems also need to satisfy additional design criteria like, e.g., energy consumption. Performing WCET and energy analyses statically at compile-time can be time-consuming. Consequently, minimizing WCET and energy consumption of the code at the compiler level using multi-objective optimization can be a time-consuming process. In this paper, we propose an approximation model to quickly approximate the WCET and energy consumption of the code at compile-time. Instead of using traditional WCET and energy analyses, we exploit this approximation model to perform ScratchPad Memory (SPM) allocation-based multi-objective optimization. Furthermore, we solve the multi-objective optimization problem using metaheuristic algorithms and explore the trade-offs between WCET and energy consumption. Using the proposed approximation model, we achieved, on average, a 94.12% reduction in compilation time and maintained the quality of the Pareto optimal solutions while performing the multi-objective optimization. Furthermore, the approximation error while using the proposed approximation model was in an acceptable range of 2% - 4% on average.}
}

@inproceedings{PFS+:2022,
Author = {Swantje Plambeck and Görschwin Fey and Jakob Schyga and Johannes Hinckeldeyn and Jochen Kreutzfeldt},
Title = {Explaining Cyber-Physical Systems Using Decision Trees.},
Year = {(2022).},
Note = {gfey, splambeck, CE},
Howpublished = {22-9997 PFS+:2022 CAADCPS},
Booktitle = {<em>Computation-Aware Algorithmic Design for Cyber-Physical Systems (CAADCPS)</em>}
}

@inproceedings{PSF:2022,
Author = {Swantje Plambeck and Lutz Schammer and Goerschwin Fey},
Title = {On the Viability of Decision Trees for Learning Models of Systems.},
Year = {(2022).},
Note = {gfey, splambeck, lschammer, CE},
Howpublished = {22-99910 PSF:2022 ASPDAC},
Booktitle = {<em>ASP Design Automation Conference (ASPDAC)</em>}
}

@inproceedings{ZFT:2021,
Author = {Ahmad Al-Zoubi and Goerschwin Fey and Konstantinos Tatas},
Title = {Resource-Aware Optimization of FPGA OpenCL Kernels.},
Year = {(2021).},
Note = {gfey, alzoubi, CE},
Howpublished = {21-999 ZFT:2021 ICEET},
Booktitle = {<em>IEEE International Conference on Engineering and Emerging Technologies (ICEET)</em>}
}

@inproceedings{GBE+:2021,
Author = {Arne Grünhagen and Julien Branlard and Annika Eichler and Gianluca Martino and Goerschwin Fey and Marina Tropmann-Frick},
Title = {Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining.},
Year = {(2021).},
Note = {gfey, gmartino, CE, agruenhagen, DASHH},
Howpublished = {21-999 GBE+:2021 ATS},
Booktitle = {<em>Asian Test Symposium (ATS)</em>}
}

@phdthesis{Oe21,
Author = {Dominic Oehlert},
Title = {Worst Case Execution Time Oriented Code Optimization of Hard Real-Time Multicore Systems.},
Year = {(2021).},
Month = {September},
Note = {doehlert, ESD, WCC},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.3855},
Howpublished = {21-78 Oe21 PHD},
Type = {PhD Thesis},
School = {Hamburg University of Technology (TUHH)},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {This thesis introduces new compiler-based optimization approaches for multi-core systems to improve their hard real-time characteristics on varying levels of abstraction. To increase scalability of optimizations and analyses with an insight into the microarchitectural level, an ILP-based derivation of shared resource access metrics is introduced. The evaluation results show, that in many cases, the optimization approaches introduced in this thesis can significantly improve the hard real-time characteristics of multi-core systems.}
}

@inproceedings{BF:2021,
Author = {Fin Hendrik Bahnsen and Goerschwin Fey},
Title = {YAPS - Your Open Examination System for Activating and emPowering Students.},
Year = {(2021).},
Note = {gfey, fbahnsen, CE},
Howpublished = {21-999 BF:2021 ICCSE},
Booktitle = {<em>IEEE International Conference on Computer Science and Education (ICCSE)</em>}
}

@inproceedings{BKF:2021,
Author = {Fin Hendrik Bahnsen and Jan Kaiser and Goerschwin Fey},
Title = {Designing Recurrent Neural Networks for Monitoring Embedded Devices.},
Year = {(2021).},
Note = {gfey, fbahnsen, CE},
Howpublished = {21-999 BKF:2021 ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@inproceedings{BKF:2021b,
Author = {Fin Hendrik Bahnsen and Vanessa Klebe and Goerschwin Fey},
Title = {Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference.},
Year = {(2021).},
Note = {gfey, fbahnsen, CE},
Howpublished = {21-999 BKF:2021b MOCAST},
Booktitle = {<em>International Conference on Circuits and Systems Technologies (MOCAST)</em>}
}

@inproceedings{MBE+:2021,
Author = {Gianluca Martino and Julien Branlard and Annika Eichler and Goerschwin Fey and Holger Schlarb},
Title = {Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems.},
Year = {(2021).},
Note = {gfey, gmartino, CE},
Howpublished = {21-999 MBE+:2021 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{MF21b,
Author = {Kateryna Muts and Heiko Falk},
Title = {Predicting Objectives on a Reduced Search Space of Multiobjective Function Inlining.},
Year = {(2021).},
Month = {November},
Note = {kmuts, hfalk, multiopt, ESD, WCC},
Isbn = {10.1145/3493229.3493303},
Howpublished = {21-70 MF21b SCOPES},
Booktitle = {<em>In Proceedings of the 24th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {The Worst-Case Execution Time (WCET), energy consumption, and code size are among the most important criteria of hard real-time systems. To estimate the WCET and energy consumption at compile time, static analyzers are often used: they estimate the objectives by invoking time-consuming microarchitecture, data flow, and control flow analyses. The expensive analyses make it almost infeasible to use evolutionary algorithms for solving multiobjective problems with these two objectives at compile time, since any evolutionary algorithm extensively evaluates objectives to find solutions. We propose a method that speeds up an evolutionary algorithm supplying it with a reduced search space and prediction model fitted on the reduced search space, so the algorithm needs to explore a smaller search space and can use fast predictions instead of time-consuming estimations to evaluate the WCET and energy consumption. The proposed approach is general enough to be used for any compiler-based optimization. We demonstrate the advantages of it solving a multiobjective function inlining problem at compile time.}
}

@inproceedings{MF21a,
Author = {Kateryna Muts and Heiko Falk},
Title = {Predicting Worst-Case Execution Times During Multi-Criterial Function Inlining.},
Year = {(2021).},
Month = {October},
Note = {kmuts, hfalk, multiopt, ESD, WCC},
Isbn = {10.1007/978-3-030-95467-3_21},
Howpublished = {21-75 MF21a LOD},
Booktitle = {<em>In Proceedings of the 7th International Conference on Machine Learning, Optimization, and Data Science (LOD)</em>},
Abstract = {In the domain of hard real-time systems, the Worst-Case Execution Time (WCET) is one of the most important design criteria. Safely and accurately estimating the WCET during a static WCET analysis is computationally demanding because of the involved data flow, control flow, and microarchitecture analyses. This becomes critical in the field of multi-criterial compiler optimizations that trade the WCET with other design objectives. Evolutionary algorithms are typically exploited to solve a multi-objective optimization problem, but they require an extensive evaluation of the objectives to explore the search space of the problem. This paper proposes a method that utilizes machine learning to build a surrogate model in order to quickly predict the WCET instead of costly estimating it using static WCET analysis. We build a prediction model that is independent of the source code and assembly code features, so a compiler can utilize it to perform any compiler-based optimization. We demonstrate the effectiveness of our model on multi-criterial function inlining, where we aim to explore trade-offs between the WCET, code size, and energy consumption at compile time.}
}

@inproceedings{SPBF:2021,
Author = {Lutz Schammer and Swantje Plambeck and Fin Hendrik Bahnsen and Goerschwin Fey},
Title = {Learning Models of Cyber-Physical Systems using Automata Learning.},
Year = {(2021).},
Note = {gfey, fbahnsen, splambeck, lschammer, CE},
Howpublished = {21-999 SPBF:2021 SE4ICPS},
Booktitle = {<em>Software Engineering for Industrial Cyber-Physical Systems (SE4ICPS)</em>}
}

@inproceedings{PMF:2021,
Author = {Swantje Plambeck and Gianluca Martino and Goerschwin Fey},
Title = {Metrics for the Evaluation of Approximate Sequential Streaming Circuits.},
Year = {(2021).},
Note = {gfey, splambeck, gmartino, CE},
Howpublished = {21-999 PMF:2021 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{PSH+:2021,
Author = {Swantje Plambeck and Jakob Schyga and Johannes Hinckeldeyn and Jochen Kreutzfeldt and Goerschwin Fey},
Title = {Automata Learning for Automated Test Generation of Real Time Localization Systems.},
Year = {(2021).},
Note = {gfey, splambeck, CE},
Howpublished = {21-999 PSH+:2021 LEAC},
Booktitle = {<em>Workshop on Machine Learning in Control (Learning in Control, LEAC)</em>}
}

@inproceedings{PSF:2021b,
Author = {Swantje Plambeck and Lutz Schammer and Goerschwin Fey},
Title = {Extended Abstract: Viability of Decision Trees for Learning Models of Systems.},
Year = {(2021).},
Note = {gfey, splambeck, lschammer, CE},
Howpublished = {21-999 PSF:2021b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@phdthesis{Lu20,
Author = {Arno Luppold},
Title = {Schedulability-Oriented Code Optimization of Hard Real-Time Multitasking Systems.},
Year = {(2020).},
Month = {July},
Note = {aluppold, ESD, WCC},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.2842},
Howpublished = {20-85 Lu20 PHD},
Type = {PhD Thesis},
School = {Hamburg University of Technology (TUHH)},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {This thesis tackles the compiler-based optimization of embedded hard real-time systems featuring multiple processes. It presents two models, based on integer-linear programming and a genetic algorithm. They can be used in order to optimize a given multitasking system specifically with respect to its timing requirements. The thesis thereby unites system-level schedulability analysis with concepts from compiler-based code optimization.}
}

@article{LOF20,
Author = {Arno Luppold, Dominic Oehlert and Heiko Falk},
Title = {Compiling for the Worst Case: Memory Allocation for Multi-task and Multi-core Hard Real-time Systems.},
Journal = {<em>ACM Transactions on Embedded Computing Systems (TECS)</em>.},
Year = {(2020).},
Volume = {<strong>19</strong>.},
Number = {(2),},
Month = {March},
Note = {aluppold, doehlert, hfalk, ESD, multiopt, teamplay, WCC},
Publisher = {ACM:},
Series = {202003-tecs-luppold.pdf},
Isbn = {10.1145/3381752},
Howpublished = {20-95 LOF20 TECS},
Abstract = {Modern embedded hard real-time systems feature multiple tasks running on multiple processing cores. Schedulability analysis of such systems is usually performed on an abstract system level with each task being represented as a black box with fixed timing properties. If timing constraints are violated, optimizing the system on a code-level in order to achieve schedulability is a tedious task. To tackle this issue, we propose an extension to the WCET-Aware C Compiler framework WCC. We integrated an optimization framework based on Integer-Linear Programming into the WCC which is able to optimize a multi-core system with multiple tasks running on each core with regards to its schedulability. We evaluate the framework by providing two approaches on a schedulability aware static Scratchpad Memory (SPM) allocation: One based on Integer-Linear Programming (ILP) and one based on a genetic algorithm.}
}

@inproceedings{OUF20,
Author = {Dominic Oehlert, Edward Umaña Williams and Heiko Falk},
Title = {Work-In-Progress: Fine-Grained On-Chip Energy Measurement of a Real-Time Multi-Core Processor.},
Year = {(2020).},
Month = {December},
Note = {doehlert, hfalk, ESD, WCC},
Series = {202012-rtss-oehlert.pdf},
Howpublished = {20-75 OUF20 RTSS},
Booktitle = {<em>In Brief Presentations of the 41st International IEEE Real-Time Systems Symposium (RTSS)</em>},
Abstract = {Embedded systems are often constrained by their energy consumption. To create energy-efficient software or to validate worst-case energy behavior, sophisticated energy models can be used. Measuring the energy consumption of a processor on a fine-grained level for an energy model typically requires the design of custom measurement hardware. In this paper we present a simple measurement setup using the on-chip ADC of a TriCore AURIX TC277 multi-core processor, utilizing one core as a measurement core without the need of external or additional HW. We show that with this setup, a reasonable level of accuracy can be achieved. Furthermore, this also enables on-line power measurements and energy-aware decisions for, e.g., mixed criticality systems.}
}

@inproceedings{BF:2020,
Author = {Fin Hendrik Bahnsen and Vanessa Klebe and Goerschwin Fey},
Title = {Emulation of Neural Networks under HW Faults.},
Year = {(2020).},
Note = {gfey, fbahnsen, vklebe, CE},
Howpublished = {20-999 BF:2020 TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{MRF:2020,
Author = {Gianluca Martino, Heinz Riener and Goerschwin Fey},
Title = {Revisiting Explicit Enumeration for Exact Synthesis.},
Year = {(2020).},
Note = {gmartino, gfey, CE},
Address = {Portorož / Slovenia},
Isbn = {10.1109/DSD51259.2020.00016},
Howpublished = {20-999 MRF:2020 DSD},
Booktitle = {<em>In Proceedings of Euromicro Conference on Digital System Design (DSD)</em>}
}

@inbook{FJL+20,
Author = {Heiko Falk, Shashank Jadhav, Arno Luppold, Kateryna Muts, Dominic Oehlert, Nina Piontek and Mikko Roth},
Title = {Compilation for Real-Time Systems a Decade After PREDATOR.},
Year = {(2020).},
Pages = {151-169},
Month = {August},
Note = {hfalk, sjadhav, aluppold, kmuts, doehlert, npiontek, mroth, ESD, emp2, multiopt, teamplay, WCC},
Editor = {In J.-J. Chen (Eds.)},
Publisher = {Springer:},
Series = {20200828-predator-springer.pdf},
Isbn = {10.1007/978-3-030-47487-4_10},
Howpublished = {20-80 FJL+20 Springer},
Booktitle = {<em>A Journey of Embedded and Cyber-Physical Systems</em>},
Abstract = {On the occasion of Peter Marwedel's 70th anniversary, this article provides a survey over a decade of research in the field of compiler techniques for real-time systems. Ten years ago, during the EU-funded project PREDATOR, it was him who led the work package on compilers. As will be shown in this survey, the work done in this domain had such a fundamental character that it laid the ground for follow-up research that lasts since the end of PREDATOR until today. This article particularly emphasizes results achieved in the challenging areas of scheduling-aware optimization of multi-task systems, of analysis and optimization of Multi-Processor Systems on Chip, and of predictable multi-objective optimizations.}
}

@article{Zi20d,
Author = {Karl-Heinz Zimmermann},
Title = {On Krohn-Rhodes Theory for Semiautomata.},
Journal = {<em>arXiv</em>.},
Year = {(2020).},
Month = {November},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/2010.16235.pdf},
Howpublished = {Zi20d},
Abstract = {Krohn-Rhodes theory encompasses the techniques for the study of finite automata and their decomposition into elementary automata. The famous result of Krohn and Rhodes roughly states that each finite automaton can be decomposed into elementary components which correspond to permutation and result automata connected by a cascade product. However, this outcome is not easy to access for the working computer scientist. This paper provides a short introduction into Krohn-Rhodes theory based on the valuable work of Ginzburg.}
}

@book{Zi20e,
Author = {Karl-Heinz Zimmermann},
Title = {Berechenbarkeit.},
Year = {(2020).},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Series = {https://arxiv.org/pdf/2010.16235.pdf},
Howpublished = {Zi20e},
Abstract = {Dieses B\"uchlein ist eine 60-seitige Einf\"uhrung in the Theorie der Berechenbarkeit. Neben Modellen der Berechenbarkeit werden wichtige unentscheidbare Entscheidungsprobleme behandelt.}
}

@book{Zi20f,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2020).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {TuBib:},
Isbn = {10.15480/882.2897},
Howpublished = {Zi20f},
Abstract = {Einf\"uhrung in die Theorie der Berechenbarkeit auf dem fortgeschrittenen Bachelor-Niveau.}
}

@inproceedings{MF20,
Author = {Kateryna Muts and Heiko Falk},
Title = {Multi-Criteria Function Inlining for Hard Real-Time Systems.},
Year = {(2020).},
Pages = {56-66},
Month = {June},
Note = {kmuts, hfalk, multiopt, ESD, WCC},
Series = {20200610-rtns-muts.pdf},
Address = {Paris / France},
Isbn = {10.1145/3394810.3394819},
Howpublished = {20-90 MF20 RTNS},
Booktitle = {<em>In Proceedings of the 28th International Conference on Real-Time Networks and Systems (RTNS)</em>},
Abstract = {Modern hard real-time systems shall satisfy some special requirements. Besides timing constraints, the additional design criteria such as code size and energy consumption are also not negligible. To optimize a system towards the mentioned specifications simultaneously is impossible, since the improvement in one of them may lead to the degradation of others. Many compiler-based optimizations techniques have been proposed to optimize an embedded application taking into account only one requirement. Nevertheless, some heuristics consider other requirements as constraints, but not many works have tried to solve a multi-objective problem in this context. We aim to extend a well-known compiler-based optimization, function inlining, to a multi-objective problem. We show that in case of such setup, the considered optimization leads to a set of trade-offs between timing constraints, code size, and energy consumption. Depending on the requirements, a system designer can utilize the output set to make a final decision about the system configuration without building an expensive hardware.}
}

@article{CaZi20c,
Author = {Mehwish Saleemi, Merve Cakir and Karl-Heinz Zimmermann},
Title = {Dynamic Programming in Topological Spaces.},
Journal = {<em>arXiv</em>.},
Year = {(2020).},
Month = {November},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/2010.12266.pdf},
Howpublished = {MeCaZi20c},
Abstract = {Dynamic programming is a mathematical optimization method and a computer programming method as well. In this paper, the notion of sheaf programming is topological spaces is introduced and it is demonstrated that it relates very well to the concept of dynamic programming.}
}

@article{CaZi20a,
Author = {Merve Cakir and Karl-Heinz Zimmermann},
Title = {Stochastic Automata over Monoids.},
Journal = {<em>arXiv</em>.},
Year = {(2020).},
Month = {January},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/2002.01214.pdf},
Howpublished = {CaZi20a},
Abstract = {Stochastic automata over monoids as input sets are studied. The well-definedness of these automata requires an extension postulate that replaces the inherent universal property of free monoids. As a generalization of Turakainen's result, it will be shown that the generalized automata over monoids have the same acceptance power as their stochastic counterparts. The key to homomorphisms is a commuting property between the monoid homomorphism of the input states and the monoid homomorphism of transition matrices. Closure properties of the languages accepted by stochastic automata over monoids are investigated.}
}

@article{CaZi20b,
Author = {Merve Cakir and Karl-Heinz Zimmermann},
Title = {On the Decomposition of Generalized Semiautomata.},
Journal = {<em>arXiv</em>.},
Year = {(2020).},
Month = {May},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/2004.08805.pdf},
Howpublished = {CaZi20b},
Abstract = {Semiautomata are abstractions of electronic devices that are deterministic finite-state machines having inputs but no outputs. Generalized semiautomata are obtained from stochastic semiautomata by dropping the restrictions imposed by probability. It is well-known that each stochastic semiautomaton can be decomposed into a sequential product of a dependent source and a deterministic semiautomaton making partly use of the celebrated theorem of Birkhoff-von Neumann. It will be shown that the each generalised semiautomaton can be partitioned into a sequential product of a generalized dependent source and a deterministic semiautomaton.}
}

@inproceedings{OLF19a,
Author = {Dominic Oehlert, Arno Luppold and Heiko Falk},
Title = {Favorable Adjustment of Periods for Reduced Hyperperiods in Real-Time Systems.},
Year = {(2019).},
Pages = {82-85},
Month = {May},
Note = {doehlert, aluppold, hfalk, multiopt, teamplay, ESD, WCC},
Series = {201905-scopes-oehlert.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/3323439.3323975},
Howpublished = {19-75 OLF19a SCOPES},
Booktitle = {<em>In Proceedings of the 22nd International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {The hyperperiod defines the time span after which the temporal behavior of a periodical real-time system repeats. It is the key property which determines the complexity of both analysis and exhaustive simulation of a given system. Unfortunately, the hyperperiod may easily become very large. We introduce an ILP-based approach to modify the periods in a task set according to user constraints to retrieve an optimal solution for a drastically reduced hyperperiod.}
}

@inproceedings{OSF19,
Author = {Dominic Oehlert, Semla Saidi and Heiko Falk},
Title = {Code-Inherent Traffic Shaping for Hard Real-Time Systems.},
Year = {(2019).},
Month = {October},
Note = {doehlert, ssaidi, hfalk, ESD, WCC, teamplay},
Series = {20191016-emsoft-oehlert.pdf},
Address = {Ney York City / USA},
Isbn = {10.1145/3358215},
Howpublished = {19-65 OSF19 EMSOFT},
Booktitle = {<em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em>},
Abstract = {Modern hard real-time systems evolved from isolated single-core architectures to complex multi-core architectures which are often connected in a distributed manner. With the increasing influence of interconnections in hard real-time systems, the access behavior to shared resources of single tasks or cores becomes a crucial factor for the system's overall worst-case timing properties. Traffic shaping is a powerful technique to decrease contention in a network and deliver guarantees on network streams. In this paper we present a novel approach to automatically integrate a traffic shaping behavior into the code of a program for different traffic shaping profiles while being as least invasive as possible. As this approach is solely depending on modifying programs on a code-level, it does not rely on any additional hardware or operating system-based functions. We show how different traffic shaping profiles can be implemented into programs using a greedy heuristic and an evolutionary algorithm, as well as their influences on the modified programs. It is demonstrated that the presented approaches can be used to decrease worst-case execution times in multi-core systems and lower buffer requirements in distributed systems.}
}

@inproceedings{BF:2019b,
Author = {Fin Hendrik Bahnsen and Goerschwin Fey},
Title = {Approximation of Neural Networks for Verification.},
Year = {(2019).},
Note = {gfey, fbahnsen, CE},
Howpublished = {19-999 BF:2019b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{BF:2019,
Author = {Fin Hendrik Bahnsen and Goerschwin Fey},
Title = {Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks.},
Year = {(2019).},
Pages = {485-491},
Note = {gfey, fbahnsen, CE},
Isbn = {10.1109/DSD.2019.00076},
Howpublished = {19-999 BF:2019 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{BF:2019c,
Author = {Fin Hendrik Bahnsen and Goerschwin Fey},
Title = {Neural Networks for Monitoring Embedded Devices.},
Year = {(2019).},
Note = {gfey, fbahnsen, CE},
Howpublished = {19-999 BF:2019c TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{MF:2019,
Author = {Gianluca Martino and Goerschwin Fey},
Title = {Syntax-Guided Enumeration of Temporal Properties.},
Year = {(2019).},
Note = {gmartino, gfey, CE},
Address = {Southampton / United Kingdom},
Isbn = {10.1109/FDL.2019.8876892},
Howpublished = {19-999 MF:2019 FDL},
Booktitle = {<em>In Proceedings of Forum on Specification and Design Languages (FDL)</em>}
}

@inproceedings{MRF:2019,
Author = {Gianluca Martino, Heinz Riener and Görschwin Fey},
Title = {Complete Specification Mining.},
Year = {(2019).},
Month = {March},
Note = {gmartino, gfey, CE},
Address = {Florence / Italy},
Howpublished = {19-999 MRF:2019 DUHDE},
Booktitle = {<em>In Proceedings of Workshop on Design Automation for Understanding Hardware Designs (DUHDE)</em>}
}

@inproceedings{FG:2019,
Author = {Goerschwin Fey and Alberto Garcia-Ortiz},
Title = {Symbolic Circuit Analysis under an Arc Based Timing Model.},
Year = {(2019).},
Note = {gfey, CE},
Isbn = {10.1109/ETS.2019.8791525},
Howpublished = {19-999 FG:2019 ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@incollection{FD:2019c,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Self-Explaining Digital Systems: Technical View, Implementation Aspects, and Completeness.},
Year = {(2019).},
Note = {gfey, CE},
Editor = {In Rolf Drechsler and Mathias Soeken (Eds.)},
Publisher = {Springer:},
Howpublished = {19-999 FD:2019c {ADVANCED BOOLEAN TECHNIQUES -- SELECTED PAPERS FROM THE 13TH INTERNATIONAL WORKSHOP ON BOOLEAN PROBLEMS}},
Booktitle = {<em>Advanced Boolean Techniques - Selected Papers from the 13th International Workshop on Boolean Problems</em>}
}

@inproceedings{FD:2019b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Self-Explaining Digital Systems - Some Technical Steps.},
Year = {(2019).},
Note = {gfey, CE},
Howpublished = {19-999 FD:2019b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@misc{FJL+19,
Author = {Heiko Falk, Shashank Jadhav, Arno Luppold, Kateryna Muts, Dominic Oehlert, Nina Piontek and Mikko Roth},
Title = {Compilation for Real-Time Systems 10 Years After PREDATOR.},
Year = {(2019).},
Month = {July},
Note = {hfalk, sjadhav, aluppold, kmuts, doehlert, npiontek, mroth, multiopt, teamplay, ESD, WCC},
Address = {Dortmund / Germany},
Howpublished = {19-70 Falk Dortmund},
Type = {Invited Talk at the Workshop on Embedded Systems, dedicated to Peter Marwedel,}
}

@book{Zimm19,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2019).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {https://tore.tuhh.de/bitstream/11420/2889/1/cc-khz-2019.pdf},
Edition = {9.},
Isbn = {10.15480/882.1714},
Howpublished = {19-65 Zimm19 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year Bachelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to present the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg.<br /> In the last edition, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complemented by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each problem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-known result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch. In the fourth and fifth editions, some small amendments have been make.}
}

@book{Zimm19a,
Author = {Karl-Heinz Zimmermann},
Title = {Curves, Cryptosystems and Quantum Computing.},
Year = {(2019).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {https://tore.tuhh.de/handle/11420/2890},
Edition = {1.},
Isbn = {10.15480/882.1714},
Howpublished = {19-65 Zimm19 TUBdok},
Abstract = {This book gives an introduction to the theory of elliptic curves and their cryptographic use. In the last part, the principles of quantum computing are introduced and the famous algorithms of Shor and Grover are presented.}
}

@inproceedings{MLF19,
Author = {Kateryna Muts, Arno Luppold and Heiko Falk},
Title = {Compiler-Based Code Compression for Hard Real-Time Systems.},
Year = {(2019).},
Pages = {72-81},
Month = {May},
Note = {kmuts, aluppold, hfalk, multiopt, ESD, WCC},
Series = {201905-scopes-muts.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/3323439.3323976},
Howpublished = {19-85 MLF19 SCOPES},
Booktitle = {<em>In Proceedings of the 22nd International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Real-Time Systems often come with additional requirements apart from being functionally correct and adhering to their timing constraints. Another common additional optimization goal is to meet code size requirements. Code compression techniques might be utilized to meet code size constraints in embedded systems. We show how to extend a compiler targeting hard real-time systems by an asymmetric compiler-based code compression/decompression, where the compression is performed at the compilation time and the decompression takes place at the execution time. Moreover, experimental results show the impact of the decompression algorithm on the estimated Worst-Case Execution Time that is one of the key properties of hard real-time systems.}
}

@article{LeZi19a,
Author = {Robert Leppert and Karl-Heinz Zimmermann},
Title = {Inference in Graded Bayesian Networks.},
Journal = {<em>arXiv</em>.},
Year = {(2019).},
Month = {January},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/1901.01837.pdf},
Howpublished = {19-90 LeZi19a},
Abstract = {Machine learning provides algorithms that can learn from data and make inferences or predictions on data. Bayesian networks are a class of graphical models that allow to represent a collection of random variables and their condititional dependencies by directed acyclic graphs. In this paper, an inference algorithm for the hidden random variables of a Bayesian network is given by using the tropicalization of the marginal distribution of the observed variables. By restricting the topological structure to graded networks, an inference algorithm for graded Bayesian networks will be established that evaluates the hidden random variables rank by rank and in this way yields the most probable states of the hidden variables. This algorithm can be viewed as a generalized version of the Viterbi algorithm for graded Bayesian networks.}
}

@article{BFG+:2019,
Author = {Roderick Bloem and Goerschwin Fey and Fabian Greif and Robert Könighofer and Ingo Pill and Heinz Riener and Franz Röck},
Title = {Synthesizing Adaptive Test Strategies from Temporal Logic Specifications.},
Journal = {<em>Formal Methods in System Design (FMSD)</em>.},
Year = {(2019).},
Note = {gfey, CE},
Isbn = {10.1007/s10703-019-00338-9},
Howpublished = {19-999 BFG+:2019 FMSD}
}

@inproceedings{JF19a,
Author = {Shashank Jadhav and Heiko Falk},
Title = {Multi-Objective Optimization for the Compiler of Real-Time Systems based on Flower Pollination Algorithm.},
Year = {(2019).},
Pages = {45-48},
Month = {May},
Note = {sjadhav, hfalk, teamplay, ESD, WCC},
Series = {201905-scopes-jadhav.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/3323439.3323977},
Howpublished = {19-80 JF19a SCOPES},
Booktitle = {<em>In Proceedings of the 22nd International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Real-time systems usually face stringent constraints such as execution time, energy consumption, code-size etc. Performing multi-objective optimization at compile time is one way to find approximations over the possible solutions which fulfill these constraints. Flower pollination algorithm (FPA) is a relatively recently proposed metaheuristic algorithm which makes use of the evolutionary characteristics of flower pollination process to find solutions to an optimization problem. In this paper, we propose a theoretical framework for an extension for the WCET-Aware C Compiler (WCC) framework for performing multi-objective optimizations based on the FPA during compile time.}
}

@inproceedings{JRF+19,
Author = {Shashank Jadhav, Mikko Roth, Heiko Falk, Christopher Brown and Adam Barwell},
Title = {Reasoning about non-functional properties using compiler intrinsic function annotations.},
Year = {(2019).},
Pages = {25-28},
Month = {November},
Note = {sjadhav, mroth, hfalk, ESD, WCC, teamplay},
Series = {20191107-jrwrtc-jadhav.pdf},
Address = {Toulouse / France},
Isbn = {10.15480/882.2545},
Howpublished = {19-60 JRF+ JRWRTC},
Booktitle = {<em>In Proceedings of the 13th Junior Researcher Workshop on Real-Time Computing (JRWRTC)</em>},
Abstract = {Embedded systems often need to adhere to time and energy constraints. With the increasing popularity of embedded systems, the interest in evaluating and optimizing non-functional properties like execution time and energy of these systems is increasing. In this paper, we describe a Resource-usage Estimate Expression Language (REEL), which allows the user to argue about these properties, within the source code, in a compiler understandable manner. Furthermore, we discuss the integration of REEL within a compiler framework. We, also show the propagation of REEL annotations within the compiler, and how they can be exploited to make decisions based on the non-functional properties within the source code. Finally, we explore REEL's potential to perform ILP-based optimizations.}
}

@inproceedings{GMD+:2019,
Author = {Tara Ghasempouri and Jan Malburg and Alessandro Danese and Graziano Pravadelli and Goerschwin Fey and Jaan Raik},
Title = {Engineering of an Effective Automatic Dynamic Assertion Mining Platform.},
Year = {(2019).},
Note = {gfey, CE},
Isbn = {10.1109/VLSI-SoC.2019.8920331},
Howpublished = {19-999 GMD+:2019 VLSISOC},
Booktitle = {<em>IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC)</em>}
}

@inproceedings{GMD+:2019b,
Author = {Tara Ghasempouri and Jan Malburg and Alessandro Danese and Graziano Pravadelli and Goerschwin Fey and Jaan Raik},
Title = {Engineering of an Effective Automatic Assertion-based Verification Platform.},
Year = {(2019).},
Note = {gfey, CE},
Howpublished = {19-999 GMD+:2019b DUHDE},
Booktitle = {<em>Workshop on Design Automation for Understanding Hardware Designs (DUHDe)</em>}
}

@article{KnZi19a,
Author = {Vincent Knapps and Karl-Heinz Zimmermann},
Title = {Distributed Monitoring of Topological Events via Homology.},
Journal = {<em>arXiv</em>.},
Year = {(2019).},
Month = {January},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/1901.04146.pdf},
Howpublished = {19-95 KnZi19a},
Abstract = {Topological event detection allows for the distributed computation of homology by focusing on local changes occurring in a network over time. In this paper, a model for the monitoring of topological events in dynamically changing regions will be developed. Regions are approximated as the connected components of the communication graph of a sensor network, reducing homology computation to graph homology. Betti number differences together with cyclic neighbor-rings are used to categorize topological event types. The focus lies on the correct detection of non-incremental (i.e., multiple concurrently occurring) events and the necessary region update process. Network number differences between a network's state before and after events are spread from event nodes into network regions, allowing for the conflict-free updating of regions independent of the update messages' order of arrival.}
}

@inproceedings{TF:2018,
Author = {Abraham Temesgen Tibebu and Goerschwin Fey},
Title = {Augmenting All Solutions SAT Solving for Circuits with Structural Information.},
Year = {(2018).},
Note = {gfey, CE},
Howpublished = {18-999 TF:2018 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@techreport{LOF18,
Author = {Arno Luppold, Dominic Oehlert and Heiko Falk},
Title = {Evaluating the Performance of Solvers for Integer-Linear Programming.},
Year = {(2018).},
Month = {November},
Note = {aluppold, doehlert, hfalk, ESD, WCC},
Series = {20181119-report-luppold.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.1839},
Howpublished = {18-55 LOF18 Hamburg},
Type = {Technical Report},
School = {Hamburg University of Technology},
Institution = {Institute of Embedded Systems},
Abstract = {Optimizing embedded systems often boils down to solving complex combinatorial optimization problems. Integer-Linear Programming (ILP) turned out to be a powerful tool to solve these problems, as beyond traditional constraints, Boolean variables may be used to model complex logical expressions and conditionals. One of the key technical aspects is to be able to efficiently express these relations within the ILP. This paper presents formalized solutions for these issues, as well as an assessment of common ILP solvers. Additionally, the performance impact is illustrated using a compiler based cache aging optimization.}
}

@inproceedings{MLF18b,
Author = {Claire Pagetti, Julien Forget, Heiko Falk, Dominic Oehlert and Arno Luppold},
Title = {Automated generation of time-predictable executables on multi-core.},
Year = {(2018).},
Pages = {104-113},
Month = {October},
Note = {aluppold, doehlert, hfalk, ESD, WCC},
Series = {20181010-rtns-pagetti.pdf},
Address = {Poitiers / France},
Isbn = {10.1145/3273905.3273907},
Howpublished = {18-60 PFFOL18 RTNS},
Booktitle = {<em>In Proceedings of the 26th International Conference on Real-Time Networks and Systems (RTNS)</em>},
Abstract = {In this paper, we are interested in the implementation of control-command applications, such as the flight control system of an aircraft for instance, on multi-core hardware. Due to certification and safety issues, time-predictability – in the sense that the timing behavior must be analysable and validable off-line – is a mandatory feature. We present a complete framework, from high-level system specification in synchronous languages, to implementation on a multi-core hardware platform, which enforces time-predictability at every step of the development process. The framework is based on automated code generation tools to speed-up the development process and to eliminate error-prone human-made translation steps.}
}

@inproceedings{OF18,
Author = {Dominic Oehlert and Heiko Falk},
Title = {WCET Analysis of Automotive Buses using WCC.},
Year = {(2018).},
Month = {March},
Note = {doehlert, hfalk, ESD, emp2, WCC},
Series = {20180323-date_npcar-oehlert.pdf},
Address = {Dresden / Germany},
Howpublished = {18-95 OF18 NPCAR},
Booktitle = {<em>In Proceedings of the DATE Workshop on New Platforms for Future Cars</em>},
Abstract = {Bus systems build the backbone of the communication systems in modern cars. This leads to the fact that the effects of these bus systems have to be included during the WCET analysis of software running on these platforms. This paper shows how two bus systems commonly used in the automotive domain can be included into the WCET analysis using the WCC.}
}

@inproceedings{OLF18a,
Author = {Dominic Oehlert, Arno Luppold and Heiko Falk},
Title = {Compilation for Real-Time Systems - An Overview of the WCET-Aware C Compiler WCC.},
Year = {(2018).},
Month = {July},
Note = {doehlert, aluppold, hfalk, ESD, WCC},
Address = {Barcelona / Spain},
Howpublished = {18-74 OLF18a WATERS},
Booktitle = {<em>In Proceedings of the 9th International Workshop on Analysis Tools and Methodologies for Embedded and Real-Time Systems (WATERS)</em>},
Abstract = {Traditionally, design of embedded hard real-time software and timing analysis are decoupled from each other, leading to complicated design flows involving human interaction. Furthermore, traditional compilers optimize for average-case performance so that no tool support exists supporting the designer to systematically reduce Worst-Case Execution Times in case that deadlines are missed. The WCET-aware C Compiler WCC improves this situation by tightly integrating timing analyses (both static WCET analyses as well as schedulability analyses) into the compilation and optimization flow. Furthermore, the compiler features dedicated real-time aware optimizations and exploits detailed architectural knowledge so that schedulable code meeting deadlines can be generated automatically, even for multi-task or multi-core systems.}
}

@inproceedings{OLF18,
Author = {Dominic Oehlert, Arno Luppold and Heiko Falk},
Title = {Mitigating Data Cache Aging through Compiler-Driven Memory Allocation.},
Year = {(2018).},
Pages = {58-61},
Month = {May},
Note = {doehlert, aluppold, hfalk, ESD, WCC},
Series = {20180528-scopes-oehlert.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/3207719.3207731},
Howpublished = {18-85 OLF18 SCOPES},
Booktitle = {<em>In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Many embedded systems have to operate flawlessly over several years. One of the key issues which may cause computational errors over time are memory errors inflicted by aging effects. We propose a compiler-based optimization in order to mitigate such effects on data caches using SRAM memory cells.}
}

@inproceedings{OSF18,
Author = {Dominic Oehlert, Selma Saidi and Heiko Falk},
Title = {Compiler-Based Extraction of Event Arrival Functions for Real-Time Systems Analysis.},
Year = {(2018).},
Pages = {4:1-4:22},
Month = {July},
Note = {doehlert, ssaidi, hfalk, ESD, WCC},
Series = {20180704-ecrts-oehlert.pdf},
Address = {Barcelona / Spain},
Isbn = {10.4230/LIPIcs.ECRTS.2018.4},
Howpublished = {18-75 OSF18 ECRTS},
Booktitle = {<em>In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS)</em>},
Abstract = {Event arrival functions are commonly required in real-time systems analysis. Yet, event arrival functions are often either modeled based on specifications or generated by using potentially unsafe captured traces. To overcome this shortcoming, we present a compiler-based approach to safely extract event arrival functions. The extraction takes place at the code-level considering a complete coverage of all possible paths in the program and resulting in a cycle accurate event arrival curve. In order to reduce the runtime overhead of the proposed algorithm, we extend our approach with an adjustable level of granularity always providing a safe approximation of the tightest possible event arrival curve. In an evaluation, we demonstrate that the required extraction time can be heavily reduced while maintaining a high precision.}
}

@inproceedings{MRF:2018,
Author = {Gianluca Martino, Heinz Riener and Görschwin Fey},
Title = {Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems.},
Year = {(2018).},
Month = {July},
Note = {gmartino, gfey, CE},
Address = {San Francisco / USA},
Howpublished = {18-999 MRF:2018 IWLS},
Booktitle = {<em>In Proceedings of International Workshop on Logic & Synthesis (IWLS)</em>}
}

@inproceedings{FGJMRR:2018,
Author = {Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik and Heinz Riener},
Title = {Design Understanding: From Logic to Specification.},
Year = {(2018).},
Note = {gmartino, gfey, CE},
Address = {Verona / Italy},
Isbn = {10.1109/VLSI-SoC.2018.8644732},
Howpublished = {18-999 FGJMRR:2018 VLSI-SoC},
Booktitle = {<em>In Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</em>}
}

@inproceedings{MRF:2018b,
Author = {Jan Malburg and Heinz Riener and Goerschwin Fey},
Title = {Mining Latency Guarantees for RTL Designs.},
Year = {(2018).},
Note = {gfey, CE},
Howpublished = {18-999 MRF:2018b ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@inproceedings{JTH+:2018,
Author = {Karl Janson and Carl Johann Treudler and Thomas Hollstein and Jaan Raik and Maksim Jenihhin and Goerschwin Fey},
Title = {Software-Level TMR Approach for On-Board Data Processing in Space Applications.},
Year = {(2018).},
Note = {gfey, CE},
Howpublished = {18-999 JTH+:2018 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@article{Zi18x,
Author = {Karl-Heinz Zimmermann},
Title = {Computations in Stochastic Acceptors.},
Journal = {<em>arXiv</em>.},
Year = {(2018).},
Month = {December},
Note = {khzimmermann, AEG},
Series = {https://arxiv.org/pdf/1812.09687.pdf},
Howpublished = {18-50 Zi18x},
Abstract = {Machine learning provides algorithms that can learn from data and make inferences or predictions on data. Stochastic acceptors or probabilistic automata are stochastic automata without output that can model components in machine learning scenarios. In this paper, we provide dynamic programming algorithms for the computation of input marginals and the acceptance probabilities in stochastic acceptors. Furthermore, we specify an algorithm for the parameter estimation of the conditional probabilities using the expectation-maximization technique and a more efficient implementation related to the Baum-Welch algorithm.}
}

@book{Zimm18,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2018).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20150722-computability-theory-zimmermann.pdf},
Edition = {8.},
Isbn = {10.15480/882.1714},
Howpublished = {18-65 Zimm18 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year Bachelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to present the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg.<br /> In the second edition, 2012, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complemented by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each problem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-known result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch. In the fourth and fifth editions, some small amendments have been make.}
}

@inproceedings{MLF18b,
Author = {Kateryna Muts, Arno Luppold and Heiko Falk},
Title = {Multi-Objective Optimization for the Compiler of Hard Real-Time Systems.},
Year = {(2018).},
Month = {July},
Note = {kmuts, aluppold, hfalk, multiopt, ESD, WCC},
Address = {Bordeaux / France},
Howpublished = {18-70 MLF18b ISMP},
Booktitle = {<em>In Proceedings of the 23rd International Symposium on Mathematical Programming (ISMP)</em>},
Abstract = {With the growing complexity of embedded systems software, high code quality can only be achieved using a compiler. Sophisticated compilers provide various optimizations to improve code aggressively w.r.t. different objective functions, e.g., worst-case execution time (WCET) and code size, which usually contradict each other. In order to find a suitable trade-off between these objectives, evolutionary multi-objective algorithms identifying Pareto optimal solutions are exploited. The thirs version of the Generalized Differential Evolution (GDE3) is currently one of the most suitable multi-objective evolutionary algorithms. However, the standard GDE3 cannot be used for solving the binary-coded optimization problems directly. A binary generalized differential evolution algorithm (BGDE) is inspired by the novel modified binary differential evolution algorithm (NMBDE) for single-objective optimization problems and GDE3. The formulas of the standard GDE3, including the mutation, crossover and selection operators, are reserved in BGDE. The probability estimation operator proposed in NMBDE is used to map real-coded vectors, generated by GDE3, to binary-coded vectors. The BGDE and multi-objective binary probability optimization algorithm (MBPOA), which is developed for binary-coded problems, are implemented in a compiler framework for hard real-time systems to perform an automatic minimization of the code size and WCET for the well-known compiler optimization function inlining. A comparison is performed the helps to determine the most suitable multi-objective optimizer.}
}

@inproceedings{MLF18a,
Author = {Kateryna Muts, Arno Luppold and Heiko Falk},
Title = {Multi-Criteria Compiler-Based Optimization of Hard Real-Time Systems.},
Year = {(2018).},
Pages = {54-57},
Month = {May},
Note = {kmuts, aluppold, hfalk, multiopt, ESD, WCC},
Series = {20180530-scopes-muts.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/3207719.3207730},
Howpublished = {18-80 MLF18a SCOPES},
Booktitle = {<em>In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Real-Time Systems often come with additional requirements apart from being functionally correct and adhering to their timing constraints. Common additional optimization goals are meeting code size requirements or the reduction of energy consumption. We show how to extend modern compiler frameworks to allow for optimizations towards multiple design criteria.}
}

@inproceedings{RLF18,
Author = {Mikko Roth, Arno Luppold and Heiko Falk},
Title = {Measuring and Modeling Energy Consumption of Embedded Systems for Optimizing Compilers.},
Year = {(2018).},
Pages = {86-89},
Month = {May},
Note = {mroth, aluppold, hfalk, teamplay, ESD, WCC},
Series = {20180529-scopes-roth.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/3207719.3207729},
Howpublished = {18-90 RLF18 SCOPES},
Booktitle = {<em>In Proceedings of the 21st International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Estimating energy consumption already during development as precisely as possible is crucial for many embedded system designs. These energy estimates should be expressed such that they can be used by subsequent automated optimizations during the compilation phase in order to minimize the expected energy consumption. In this paper we present our current approach on measuring and modeling, and subsequently using the derived energy estimates. Our model is implemented within an optimizing compiler, allowing for future energy focused compiler optimizations.}
}

@inproceedings{LuFa17a,
Author = {Arno Luppold and Heiko Falk},
Title = {Schedulability-Aware SPM Allocation for Preemptive Hard Real-Time Systems with Arbitrary Activation Patterns.},
Year = {(2017).},
Pages = {1074-1079},
Month = {March},
Note = {aluppold, hfalk, ESD, emp2, tacle, WCC},
Series = {201703-date-luppold.pdf},
Address = {Lausanne / Switzerland},
Isbn = {10.23919/DATE.2017.7927149},
Howpublished = {17-90 LuFa17a DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Abstract = {In hard real-time multi-tasking systems each task has to meet its deadline under any circumstances. If one or several tasks violate their timing constraints, compiler optimizations can be used to optimize the Worst-Case Execution Time (WCET) of each task with a focus on the system's schedulability. Existing approaches are limited to single-tasking or strictly periodic multi-tasking systems. We propose a compiler optimization to perform a schedulability-aware static instruction Scratchpad Allocation for arbitrary activation patterns and deadlines. The approach is based on Integer-Linear Programming and is evaluated for the Infineon TriCore TC1796 microcontroller.}
}

@inproceedings{OLF17,
Author = {Dominic Oehlert, Arno Luppold and Heiko Falk},
Title = {Bus-aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems.},
Year = {(2017).},
Pages = {1:1-1:22},
Month = {June},
Note = {doehlert, aluppold, hfalk, ESD, emp2, WCC},
Series = {20170628-ecrts-oehlert.pdf},
Address = {Dubrovnik / Croatia},
Isbn = {10.4230/LIPIcs.ECRTS.2017.1},
Howpublished = {17-80 OLF17 ECRTS},
Booktitle = {<em>In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS)</em>},
Abstract = {Over the past years, multicore systems emerged into the domain of hard real-time systems. These systems introduce common buses and shared memories which heavily influence the timing behavior. We show that existing WCET optimizations may lead to suboptimal results when applied to multicore setups. Additionally we provide both a genetic and a precise Integer Linear Programming (ILP) based static instruction scratchpad memory allocation optimization which are capable of exploiting multicore properties, resulting in a WCET reduction of 26% in average compared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimization's average runtime is distinctively lower in comparison to the genetic approach. Although limiting the number of tasks per core to one and partially exploiting private instruction SPMs, we cover the most crucial elements of a multicore setup: the interconnection and shared resources.}
}

@inproceedings{PRDC17,
Author = {Eberle Rambo, Selma Saidi and Rolf Ernst},
Title = {Designing Networks-on-Chip for High Assurance Real-Time Systems.},
Year = {(2017).},
Month = {January},
Note = {ssaidi, ESD},
Address = {Christchurch / New Zealand},
Howpublished = {17-95 RSE17 PRDC},
Booktitle = {<em>In Proceedings of the International Symposium on Dependable computing (PRDC)</em>},
Abstract = {Conventional fault-tolerance approaches for Networks-on-Chip (NoCs) cannot be applied to high assurance real-time systems due to their different goals and constraints. These systems impose strict integrity, resilience and real-time requirements. All possible effects of hardware errors must be taken into account and the resulting system must be predictable, even in the presence of errors. In this paper, we present a wormhole-switched NoC with virtual channels for high assurance real-time systems hardened against soft errors. All possible duration and impacts of soft errors are taken into account and the resulting NoC operates with formal guarantees. Experimental evaluation shows that the network is able to provide a predictable behavior even in aggressive environments with very high error rates.}
}

@article{AF:2017,
Author = {Gökçe Aydos and Goerschwin Fey},
Title = {Empirical Results on Parity-based Soft Error Detection with Software-based Retry.},
Journal = {<em>Microprocessors and Microsystems (MICPRO)</em>.},
Year = {(2017).},
Pages = {62-68},
Note = {gfey, CE},
Isbn = {10.1016/j.micpro.2016.09.009},
Howpublished = {17-999 AF:2017 MICPRO}
}

@misc{Falk17b,
Author = {Heiko Falk},
Title = {Timing Analysis and Code Optimization for Massively-Parallel Real-Time Systems.},
Year = {(2017).},
Month = {October},
Note = {hfalk, ESD, WCC},
Address = {Stuttgart / Germany},
Howpublished = {17-70 Falk CSW},
Type = {Invited Talk at the HiPEAC Autumn Computing Systems Week (CSW),}
}

@misc{Falk17a,
Author = {Heiko Falk},
Title = {Compilation Techniques for Parallel, Safety-Critical Systems with Real-Time Constraints.},
Year = {(2017).},
Month = {October},
Note = {hfalk, ESD, WCC},
Address = {Seoul / South Korea},
Howpublished = {17-75 Falk ESWEEK},
Type = {Tutorial at the Embedded Systems Week (ESWEEK),}
}

@inproceedings{RF:2017b,
Author = {Heinz Riener and Goerschwin Fey},
Title = {Computing Exact Fault Candidates Incrementally.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 RF:2017b DUHDE},
Booktitle = {<em>Workshop on Design Automation for Understanding Hardware Designs (DUHDe)</em>}
}

@inproceedings{RKFB:2016,
Author = {Heinz Riener and Robert Koenighofer and Goerschwin Fey and Roderick Bloem},
Title = {SMT-Based CPS Parameter Synthesis.},
Year = {(2017).},
Pages = {126-133},
Note = {gfey, CE},
Howpublished = {17-999 RKFB:2016 ARCH},
Booktitle = {<em>Applied Verification for Continuous and Hybrid Systems (ARCH)</em>}
}

@inproceedings{REF:2017,
Author = {Heinz Riener and Rüdiger Ehlers and Goerschwin Fey},
Title = {CEGAR-Based EF Synthesis of Boolean Functions with an Application to Circuit Rectification.},
Year = {(2017).},
Pages = {251-256},
Note = {gfey, CE},
Howpublished = {17-999 REF:2017 ASPDAC},
Booktitle = {<em>ASP Design Automation Conference (ASPDAC)</em>}
}

@inproceedings{REF:2017b,
Author = {Heinz Riener and Ruediger Ehlers and Goerschwin Fey},
Title = {Counterexample-Guided EF Synthesis of Boolean Functions.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 REF:2017b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{MRF:2017,
Author = {Jan Malburg and Heinz Riener and Goerschwin Fey},
Title = {Mining Latency Guarantees for RT-level Designs.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 MRF:2017 DUHDE},
Booktitle = {<em>Workshop on Design Automation for Understanding Hardware Designs (DUHDe)</em>}
}

@inproceedings{MFF:2017,
Author = {Jan Malburg and Tino Flenker and Goerschwin Fey},
Title = {Property Mining using Dynamic Dependency Graphs.},
Year = {(2017).},
Pages = {244-250},
Note = {gfey, CE},
Howpublished = {17-999 MFF:2017 ASPDAC},
Booktitle = {<em>ASP Design Automation Conference (ASPDAC)</em>}
}

@book{Zimm17,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2017).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20150722-computability-theory-zimmermann.pdf},
Edition = {7.},
Isbn = {10.15480/882.1401},
Howpublished = {17-65 Zimm17 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year B achelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to pr esent the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg.<br /> In the second edition, 2012, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complemented by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each problem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-known result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch. In the fourth and fifth editions, some small amendments have been make.}
}

@inproceedings{MSF:2017,
Author = {Meß, Jan-Gerd and Schmidt, Robert and Fey, Goerschwin},
Title = {Adaptive Compression Schemes for Housekeeping Data.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 MSF:2017 AEROCONF},
Booktitle = {<em>IEEE Aerospace Conference (AEROCONF)</em>}
}

@inproceedings{TF:2017,
Author = {Niels Thole and Goerschwin Fey},
Title = {Empirical Evaluation of a Formal Conservative Analysis to Prove Robustness under Variability.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 TF:2017 TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inbook{MFN17,
Author = {Peter Marwedel, Heiko Falk, and Olaf Neugebauer},
Title = {Memory-Aware Optimization of Embedded Software for Multiple Objectives.},
Year = {(2017).},
Month = {June},
Note = {hfalk, ESD, multiopt, WCC},
Editor = {In S. Ha and J. Teich (Eds.)},
Publisher = {Springer:},
Isbn = {10.1007/978-94-017-7358-4_27-2},
Howpublished = {17-85 MFN17 Springer},
Booktitle = {<em>Handbook of Hardware/Software Codesign</em>},
Abstract = {Information processing in Cyber-Physical Systems (CPSs) has to respect a variety of constraints and objectives such as response and execution time, energy consumption, Quality of Service (QoS), size and cost. Due to the large impact of the size of memories on their energy consumption and access times, an exploitation of memory characteristics offers a large potential for optimizations. In this chapter, we will describe optimization approaches proposed by our research groups. We will start with optimizations for single objectives, such as energy consumption and execution time. As a consequence of considering hard real-time systems, special attention is on the minimization of the Worst-Case Execution Time (WCET) within compilers. Three WCET reduction techniques are analyzed: exploitation of scratchpads, instruction cache locking, and cache partitioning for multi-task systems. The last section presents an approach for considering trade-offs between multiple objectives in the design of a cyber-physical sensor system for the detection of bio-viruses.}
}

@unpublished{SGF:2017b,
Author = {Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey},
Title = {Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 SGF:2017b IOLTS},
Booktitle = {<em>IEEE International On-Line Testing Symposium (IOLTS)</em>}
}

@inproceedings{SGF:2017,
Author = {Robert Schmidt and Alberto Garcia-Ortiz and Goerschwin Fey},
Title = {Temporal Redundancy Latch-based Architecture for Soft Error Mitigation.},
Year = {(2017).},
Pages = {240-243},
Note = {gfey, CE},
Isbn = {10.1109/IOLTS.2017.8046245},
Howpublished = {17-999 SGF:2017 IOLTS},
Booktitle = {<em>IEEE International On-Line Testing Symposium (IOLTS)</em>}
}

@article{ASVF:2017,
Author = {Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey},
Title = {A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.},
Journal = {<em>Journal of Electronic Testing: Theory and Applications (JETTA)</em>.},
Year = {(2017).},
Pages = {53-64},
Note = {gfey, CE},
Isbn = {10.1007/s10836-016-5637-6},
Howpublished = {17-999 ASVF:2017 JETTA}
}

@inproceedings{FF:2017,
Author = {Tino Flenker and Goerschwin Fey},
Title = {Mapping Abstract and Concrete Hardware Models for Design Understanding.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 FF:2017 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{FMF+:2017,
Author = {Tino Flenker and Jan Malburg and Görschwin Fey and Serhiy Avramenko and Massimo Violante and Matteo Sonza Reorda},
Title = {Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.},
Year = {(2017).},
Note = {gfey, CE},
Howpublished = {17-999 FMF+:2017 ISVLSI},
Booktitle = {<em>IEEE Annual Symposium on VLSI (ISVLSI)</em>}
}

@inproceedings{KTSE16a,
Author = {Adam Kostrzewa, Sebastian Tobuschat, Selma Saidi and Rolf Ernst},
Title = {Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chips.},
Year = {(2016).},
Pages = {215-224},
Month = {October},
Note = {ssaidi, ESD},
Address = {Brest / France},
Isbn = {10.1145/2997465.2997466},
Howpublished = {16-20 KTSE16 RTNS},
Booktitle = {<em>In Proceedings of the 24th International Conference on Real-Time Networks and Systems (RTNS)</em>},
Abstract = {In the majority of safety critical systems, suspension-based locking protocols e.g. MPCP, OMLP, FMLP are used to efficiently and safely coordinate accesses to shared resources. However, existing architectures do not support such arbitration for Networks-on-Chip (NoCs) although they must resolve conflicts between concurrent transmissions. Enabling suspensions requires not only predictable transmission latencies but also to provide feedback about the global state of the interconnect which is difficult in NoCs where arbitration is done locally and independently in routers. This leads to pessimistic formal guarantees, decreased utilization and unfulfilled design requirements as network blocking unnecessarily propagates to other tasks scheduled on cores. In this work, we evaluate existing NoC architectures and propose extensions allowing to benefit from real-time tasks multithreading to increase performance while achieving predictability. Consequently, we describe how to improve the processor's utilization and more importantly, how to consistently reach lower worst case latencies for other tasks running in the system. We demonstrate the effectiveness of our approach using formal analysis and scenario-based simulation results.}
}

@inproceedings{KTSE16b,
Author = {Adam Kostrzewa, Sebastian Tobuschat, Selma Saidi and Rolf Ernst},
Title = {Safe and Dynamic Traffic Rate Control for Networks-on-Chips.},
Year = {(2016).},
Pages = {1-8},
Month = {August},
Note = {ssaidi, ESD},
Address = {Nara / Japan},
Howpublished = {16-30 KTSE16b NoCS},
Booktitle = {<em>In Proceedings of the 10th International Symposium on Networks-on-Chip (NOCS)</em>},
Abstract = {Networks-on-Chip (NoCs) for real-time systems require solutions for a safe and predictable sharing of resources between transmissions with different quality-of service (QoS) requirements. In this work, we present a mechanism which allows to apply existing wormhole-switched and performance optimized NoCs in safety critical domains, without requiring complex hardware modifications. For this purpose, we introduce a global and dynamic admission control mechanism implemented in the form of an access layer, controlling the rates at which running applications can access the NoC. The mechanism allows to enforce behavioral models for different data streams as well as to dynamically adapt the rates values to the number of currently active applications. We prove this important feature using formal timing analysis. Our approach results in a higher performance and tighter guarantees while simultaneously decreasing hardware (up to 60\%) and temporal overhead (up to 80\%) when compared with existing solutions.}
}

@inproceedings{KSE16b,
Author = {Adam Kostrzewa, Selma Saidi and Rolf Ernst},
Title = {Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network.},
Year = {(2016).},
Pages = {37-46},
Month = {October},
Note = {ssaidi, ESD},
Address = {Pittsburgh / USA},
Howpublished = {16-25 KSE16b ESTIMedia},
Booktitle = {<em>In Proceedings of the 14th ACM/IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)</em>},
Abstract = {Networks-on-Chip (NoCs) for contemporary multiprocessors systems must integrate complex multimedia applications which require not only high performance but also timing guarantees. However, in existing NoCs, designed for real-time systems, timing constraints are frequently implemented at the cost of decreased hardware utilization, i.e strict spatial or temporal isolation between transmissions. In this work, we propose an alternative - multi-path scheduling (MPS) - mechanism exploiting the multidimensional structure of NoCs, to combine the path selection and the temporal flow control based on the global state of the system. Consequently, MPS allows a safe sharing of NoC resources while preserving a high utilization achieved through a predictable load distribution of data traffic among different paths, reachable from source to destination. We demonstrate using benchmarks, that MPS not only provides higher average performance compared to existing solutions, but also allows to provide worst-case guarantees. We prove this important feature using formal timing analysis. Moreover, MPS induces a low implementation overhead as it can be applied to many existing wormhole-switched and performance optimized NoCs without requiring complex hardware modifications.}
}

@inproceedings{KSE16,
Author = {Adam Kostrzewa, Selma Saidi and Rolf Ernst},
Title = {Slack-based resource arbitration for real-time Networks-on-Chip.},
Year = {(2016).},
Pages = {1012-1017},
Month = {January},
Note = {ssaidi, ESD},
Address = {Dresden / Germany},
Howpublished = {16-90 KSE16a DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Abstract = {Networks-on-Chip (NoCs) designed for real-time systems must efficiently deal with a broad diversity of traffic requirements. This requires providing latency guarantees for hard real-time transmissions with minimum impact on performance sensitive best-effort traffic. In this work, we present a novel mechanism which achieves this goal through a slack-based global and dynamic prioritization of data streams. This is performed using an overlay network and a scheduling unit combining local arbitration performed in routers with global scheduling of entire logical transmissions for end to end guarantees. Consequently, our approach allows to decrease both hardware and temporal overhead when compared with existing solutions and to achieve a performance improvement up to around 60%.}
}

@inproceedings{KSEE16,
Author = {Adam Kostrzewa, Selma Saidi, Leonardo Ecco and Rolf Ernst},
Title = {Dynamic admission control for real-time networks-on-chips.},
Year = {(2016).},
Pages = {719-724},
Month = {January},
Note = {ssaidi, ESD},
Address = {Macao},
Howpublished = {16-85 KSEE16 ASPDAC},
Booktitle = {<em>In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC)</em>},
Abstract = {Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality-of service requirementrs. In this work, we present a mechanism for a global and dynamic admission control in NoCs designed for realtime systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of system's utilization. Our mechanism does not require modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.}
}

@inproceedings{BEZWT16,
Author = {Andreas Becher, Jorge Echavaria, Daniel Ziener, Stefan Wildermann and J&uuml;rgen Teich},
Title = {A LUT-Based Approximate Adder.},
Year = {(2016).},
Month = {May},
Note = {dziener, ESD},
Address = {Washington DC / USA},
Isbn = {10.1109/FCCM.2016.16},
Howpublished = {16-65 BEZWT16 FCCM},
Booktitle = {<em>In Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)</em>},
Abstract = {In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.}
}

@inproceedings{LKF16,
Author = {Arno Luppold, Christina Kittsteiner and Heiko Falk},
Title = {Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems.},
Year = {(2016).},
Pages = {77-85},
Month = {May},
Note = {aluppold, hfalk, ESD, emp2, tacle, WCC},
Series = {20160524-scopes-luppold.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/2906363.2906369},
Howpublished = {16-75 LKF16 SCOPES},
Booktitle = {<em>In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. <br /> We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.}
}

@article{ZBBDMSTVW16,
Author = {Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Sch&uuml;rfeld, J&uuml;rgen Teich, J&ouml;rg-Stephan Vogt and Helmut Weber},
Title = {FPGA-Based Dynamically Reconfigurable SQL Query Processing.},
Journal = {<em>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</em>.},
Year = {(2016).},
Volume = {<strong>9</strong>.},
Number = {(4),},
Pages = {25:1-25:24},
Month = {August},
Note = {dziener, ESD},
Publisher = {ACM:},
Isbn = {10.1145/2845087},
Howpublished = {16-35 ZBBDMSTVW16 TRETS},
Abstract = {In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row- as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.}
}

@inbook{KZH16,
Author = {Dirk Koch, Daniel Ziener and Frank Hannig},
Title = {FPGA versus Software Programming: Why, When, and How?.},
Year = {(2016).},
Pages = {1-21},
Month = {June},
Note = {dziener, ESD},
Editor = {In Dirk Koch, Frank Hannig and Daniel Ziener (Eds.)},
Publisher = {Springer:},
Isbn = {10.1007/978-3-319-26408-0_1},
Howpublished = {16-55 KZH16 Springer},
Booktitle = {<em>FPGAs for Software Programmers</em>},
chapter = {1},
Abstract = {This chapter provides background information for readers who are interested in the philosophy and technology behind FPGAs. We present this from a software engineer’s viewpoint without hiding the hardware specific characteristics of FPGAs. The chapter discusses the architecture and programming models as well as the pros and cons of CPUs, GPUs and FPGAs. The operation of FPGAs will be described as well as the major steps that are needed to map a circuit description on an FPGA. This will provide a deep enough understanding of the characteristics of an FPGA and how this helps in accelerating certain parts of an application.}
}

@book{KHZ16,
Author = {Dirk Koch, Frank Hannig and Daniel Ziener},
Title = {FPGAs for Software Programmers.},
Year = {(2016).},
Month = {June},
Note = {dziener, ESD},
Publisher = {Springer:},
Isbn = {10.1007/978-3-319-26408-0},
Howpublished = {16-60 KHZ16 Springer},
Abstract = {This book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavioural synthesis, domain-specific compilation, and FPGA overlays.<br /> Introduces FPGA technology to software developers by giving an overview of FPGA programming models and design tools, as well as various application examples;<br /> Provides a holistic analysis of the topic and enables developers to tackle the architectural needs for Big Data processing with FPGAs;<br /> Explains the reasons for the energy efficiency and performance benefits of FPGA processing;<br /> Provides a user-oriented approach and a sense for where and how to apply FPGA technology.}
}

@inproceedings{OLK16,
Author = {Dominic Oehlert, Arno Luppold and Heiko Falk},
Title = {Practical Challenges of ILP-based SPM Allocation Optimizations.},
Year = {(2016).},
Pages = {86-89},
Month = {May},
Note = {doehlert, aluppold, hfalk, ESD, emp2, tacle, WCC},
Series = {20160524-scopes-oehlert.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/2906363.2906371},
Howpublished = {16-70 OLK16 SCOPES},
Booktitle = {<em>In Proceedings of the 19th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Scratchpad Memory (SPM) allocation is a well-known technique for compiler-based code optimizations. Integer-Linear Programming has been proven to be a powerful technique to determine which parts of a program should be moved to the SPM. Although the idea is quite straight-forward in theory, the technique features several challenges when being applied to modern embedded systems. In this paper, we aim to bring out the main issues and possible solutions which arise when trying to apply those optimizations to existing hardware platforms.}
}

@inproceedings{RSE16,
Author = {Eberle Rambo, Selma Saidi and Rolf Ernst},
Title = {Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip.},
Year = {(2016).},
Pages = {103-108},
Month = {January},
Note = {ssaidi, ESD},
Address = {Dresden / Germany},
Howpublished = {16-95 RSE16 DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Abstract = {Networks-on-Chip (NoCs) are the backbone of Multiprocessor Systems-on-Chip (MPSoCs). In this paper, we perform a formal worst-case communication time analysis of Automatic Repeat reQuest (ARQ) protocols for NoCs. Therefore we integrate the transport layer analysis for general networks and the network layer analysis for NoCs. An ARQ variant optimized for DMA transfers (DMA ARQ) is introduced and analyzed. Experimental evaluation with Stop-and-Wait, Go-Back-N, and DMA ARQ, in the context of real-time memory traffic is presented, including both error-free and error cases. DMA ARQ achieves a factor 6 improvement on latency bounds over conventional Stop-and-Wait.}
}

@inproceedings{AAB+:2016,
Author = {Gadi Aleksandrowicz and Eli Arbel and Roderick Bloem and Timon ter Braak and Sergei Devadze and Goerschwin Fey and Maksim Jenihhin and Artur Jutman and Hans G. Kerkhoff and Robert Könighofer and Jan Malburg and Shiri Moran and Jaan Raik and Gerard Rauwerda and Heinz Riener and Franz Röck and Konstantin Shibin and Kim Sunesen and Jinbo Wan and Yong Zhao},
Title = {Designing Reliable Cyber-Physical Systems.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 AAB+:2016 FDL},
Booktitle = {<em>Forum on Specification and Design Languages (FDL)</em>}
}

@unpublished{FR:2016,
Author = {Goerschwin Fey and Jaan Raik (Organizers)},
Title = {Designing Reliable Cyber-Physical Systems.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 FR:2016 FDL},
Booktitle = {<em>Forum on Specification and Design Languages (FDL)</em>}
}

@inproceedings{AF:2016b,
Author = {Gökçe Aydos and Goerschwin Fey},
Title = {Exploiting Error Detection Latency for Parity-based Soft Error Detection.},
Year = {(2016).},
Note = {gfey, CE},
Isbn = {10.1109/DDECS.2016.7482440},
Howpublished = {16-999 AF:2016b DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@misc{Falk16b,
Author = {Heiko Falk},
Title = {Achieving Timing Predictability by Combining Models.},
Year = {(2016).},
Month = {November},
Note = {hfalk, ESD, emp2},
Address = {Schloss Dagstuhl / Germany},
Howpublished = {16-15 Falk16b Dagstuhl},
Type = {Invited Talk at the Dagstuhl Seminar 16441 on Adaptive Isolation for Predictability and Security,}
}

@misc{Falk16a,
Author = {Heiko Falk},
Title = {WCET-Aware Compilation and Optimization for Real-Time Systems.},
Year = {(2016).},
Month = {June},
Note = {hfalk, ESD, emp2, WCC},
Address = {Grenoble / France},
Howpublished = {16-50 Falk16a VERIMAG},
Type = {Invited Talk at the VERIMAG Laboratory, University Grenoble Alpes,}
}

@misc{FaLu16,
Author = {Heiko Falk and Arno Luppold},
Title = {Schedulability-Aware Code Optimization for Multi-Task Real-Time Systems.},
Year = {(2016).},
Month = {March},
Note = {hfalk, aluppold, ESD, emp2, WCC},
Address = {Paris / France},
Howpublished = {16-80 FaLu16 RT-Workshop},
Type = {Invited Talk at the Workshop on Analysis vs. Synthesis in Embedded Systems Design,}
}

@inproceedings{FAH+16,
Author = {Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Bj&ouml;rn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo S&oslash;rensen, Peter W&auml;gemann and Simon Wegener},
Title = {TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research.},
Year = {(2016).},
Pages = {2:1-2:10},
Month = {July},
Note = {hfalk, ESD, tacle, taclebench},
Series = {20160705-wcet-falk.pdf},
Address = {Toulouse / France},
Isbn = {10.4230/OASIcs.WCET.2016.2},
Howpublished = {16-40 FAH+16 WCET},
Booktitle = {<em>In Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, to make the research experimentation repeatable those programs shall be made publicly available. <br /> We collected open-source programs, adapted them to a common coding style, and provide the collection in open-source. The benchmark collection is called TACLeBench and is available from GitHub in version 1.9 at the publication date of this paper. One of the main features of TACLeBench is that all programs are self-contained without any dependencies on standard libraries or an operating system.}
}

@article{RHF+:2016,
Author = {Heinz Riener and Finn Haedicke and Stefan Frehse and Mathias Soeken and Daniel Große and Rolf Drechsler and Goerschwin Fey},
Title = {metaSMT: Focus On Your Application And Not On Solver Integration.},
Journal = {<em>International Journal on Software Tools for Technology Transfer (STTT)</em>.},
Year = {(2016).},
Pages = {1-17},
Note = {gfey, CE},
Isbn = {10.1007/s10009-016-0426-1},
Howpublished = {16-999 RHF+:2016 STTT}
}

@inproceedings{RF:2016,
Author = {Heinz Riener and Goerschwin Fey},
Title = {Exact Diagnosis using Boolean Satisfiability.},
Year = {(2016).},
Pages = {53:1-53:8},
Note = {gfey, CE},
Isbn = {10.1145/2966986.2967036},
Howpublished = {16-999 RF:2016 ICCAD},
Booktitle = {<em>IEEE/ACM Int'l Conf. on CAD (ICCAD)</em>}
}

@inproceedings{RF:2016c,
Author = {Heinz Riener and Goerschwin Fey},
Title = {Counterexample-Guided Diagnosis.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 RF:2016c IVSW},
Booktitle = {<em>International Verification and Security Workshop (IVSW)</em>}
}

@unpublished{HRFS:2016b,
Author = {Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken},
Title = {Multilevel Design Understanding: From Specification to Logic (Special Session).},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 HRFS:2016b ICCAD},
Booktitle = {<em>IEEE/ACM Int'l Conf. on CAD (ICCAD)</em>}
}

@inproceedings{FHRS:2016,
Author = {Ian Harris and Sandip Ray and Goerschwin Fey and Mathias Soeken},
Title = {Multilevel Design Understanding: From Specification to Logic.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 FHRS:2016 ICCAD},
Booktitle = {<em>IEEE/ACM Int'l Conf. on CAD (ICCAD)</em>}
}

@article{MFF:2016,
Author = {Jan Malburg and Alexander Finder and Goerschwin Fey},
Title = {Debugging hardware designs using dynamic dependency graphs.},
Journal = {<em>Microprocessors and Microsystems (MICPRO)</em>.},
Year = {(2016).},
Pages = {347-359},
Note = {gfey, CE},
Howpublished = {16-999 MFF:2016 MICPRO}
}

@inproceedings{MFF:2016b,
Author = {Jan Malburg and Tino Flenker and Goerschwin Fey},
Title = {Generating Good Properties from a Small Number of Use Cases.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 MFF:2016b IVSW},
Booktitle = {<em>International Verification and Security Workshop (IVSW)</em>}
}

@inproceedings{MSFD:2016,
Author = {Jan-Gerd Meß and Robert Schmidt and Goerschwin Fey and Frank Dannemann},
Title = {On the Compression of Spacecraft Housekeeping Data using Discrete Cosine Transforms.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 MSFD:2016 TTC},
Booktitle = {<em>ESA International Tracking, Telemetry and Command Systems for Space Applications (TTC)</em>}
}

@inproceedings{EWBTZ16,
Author = {Jorge Echavaria, Stefan Wildermann, Andreas Becher, J&uuml;rgen Teich and Daniel Ziener},
Title = {FAU: Fast Approximate Adder Units on LUT-Based FPGAs.},
Year = {(2016).},
Month = {December},
Note = {dziener, ESD},
Address = {Xi'an / China},
Howpublished = {16-05 EWBTZ16 FPT},
Booktitle = {<em>In Proceedings of the International Conference on Field Programmable Technology (FPT)</em>}
}

@book{Zimm16,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2016).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20150722-computability-theory-zimmermann.pdf},
Edition = {6.},
Isbn = {10.15480/882.1309},
Howpublished = {16-100 Zimm16 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year B achelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to pr esent the basic results of computability theory, including mathematical models of computability, primitive recursive and parti al recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, un decidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during h is studies at the University of Erlangen-Nuremberg.<br /> In the second edition, 2012, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complement ed by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each pro blem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-kn own result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch. In the fourth and fifth editions, some small amendments have been make.}
}

@inproceedings{TRF:2016,
Author = {Niels Thole and Heinz Riener and Goerschwin Fey},
Title = {Equivalence Checking on ESL Utilizing A Priori Knowledge.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 TRF:2016 FDL},
Booktitle = {<em>Forum on Specification and Design Languages (FDL)</em>}
}

@inproceedings{TAF:2016b,
Author = {Niels Thole and Lorena Anghel and Goerschwin Fey},
Title = {A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.},
Year = {(2016).},
Pages = {278-283},
Note = {gfey, CE},
Isbn = {10.1109/ISVLSI.2016.106},
Howpublished = {16-999 TAF:2016b ISVLSI},
Booktitle = {<em>IEEE Annual Symposium on VLSI (ISVLSI)</em>}
}

@inproceedings{TAF:2016,
Author = {Niels Thole and Lorena Anghel and Goerschwin Fey},
Title = {A Hybrid Algorithm to Conservatively Check the Robustness of Circuits (extended abstract).},
Year = {(2016).},
Pages = {2},
Note = {gfey, CE},
Isbn = {10.1109/ETS.2016.7519326},
Howpublished = {16-999 TAF:2016 ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@inproceedings{TAF:2016c,
Author = {Niels Thole and Lorena Anghel and Goerschwin Fey},
Title = {A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 TAF:2016c TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{KRF:2016,
Author = {Niklas Krafczyk and Heinz Riener and Goerschwin Fey},
Title = {WCET Overapproximation for Software in the Context of a Cyber-Physical System.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 KRF:2016 VLSISOC},
Booktitle = {<em>IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC)</em>}
}

@article{Zimm2016-01,
Author = {Sallam Abualhaija, Karl-Heinz Zimmermann},
Title = {D-Bees: A novel method inspired by bee colony optimization for solving word sense disambiguation.},
Journal = {<em>Swarm and Evolutionary Computation</em>.},
Year = {(2016).},
Volume = {<strong>27</strong>.},
Pages = {188-195},
Note = {khzimmermann, AEG},
Isbn = {10.1016/j.swevo.2015.12.002},
Howpublished = {Zim2016-01}
}

@inproceedings{ASVF:2016,
Author = {Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey},
Title = {Analysis of the Effects of Soft Errors on Compression Algorithms Through Fault Injection Inside Program Variables.},
Year = {(2016).},
Pages = {14-19},
Note = {gfey, CE},
Isbn = {10.1109/LATW.2016.7483332},
Howpublished = {16-999 ASVF:2016 LATS},
Booktitle = {<em>IEEE Latin-American Test Symposium (LATS)</em>}
}

@inproceedings{ASV+:2016,
Author = {Serhiy Avramenko and Matteo Sonza Reorda and Massimo Violante and Goerschwin Fey and Jan-Gerd Meß and Robert Schmidt},
Title = {On the robustness of compression algorithms for space applications.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 ASV+:2016 IOLTS},
Booktitle = {<em>IEEE International On-Line Testing Symposium (IOLTS)</em>}
}

@inproceedings{PZ6,
Author = {Thorbj&ouml;rn Posewsky and Daniel Ziener},
Title = {Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing.},
Year = {(2016).},
Month = {December},
Note = {dziener, tposewsky, ESD},
Series = {201612-reconfig-posewsky.pdf},
Address = {Cancun / Mexico},
Howpublished = {16-10 PZ6 Reconfig},
Booktitle = {<em>In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</em>},
Type = {<strong>Best Paper Award</strong>.},
Abstract = {Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose a novel architecture for processing previously learned and arbitrary deep neural networks on FPGA-based SoCs that is able to overcome these limitations. A key contribution of our approach, which we refer to as batch processing, achieves a mitigation of required weight matrix transfers from external memory by reusing weights across multiple input samples. This technique combined with a sophisticated pipelining and the usage of high performance interfaces accelerates the data processing compared to existing approaches on the same FPGA device by one order of magnitude. Furthermore, we achieve a comparable data throughput as a fully featured x86-based system at only a fraction of its energy consumption.}
}

@inproceedings{FF:2016,
Author = {Tino Flenker and Goerschwin Fey},
Title = {Matching Abstract and Concrete Hardware Models for Design Understanding.},
Year = {(2016).},
Note = {gfey, CE},
Howpublished = {16-999 FF:2016 DUHDE},
Booktitle = {<em>Workshop on Design Automation for Understanding Hardware Designs (DUHDe)</em>}
}

@inproceedings{BOG16,
Author = {Wolfgang B&uuml;ter, Dominic Oehlert and Alberto Garc&iacute;a-Ortiz},
Title = {ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition.},
Year = {(2016).},
Pages = {1-6},
Month = {June},
Note = {doehlert, ESD},
Address = {Tallinn / Estonia},
Isbn = {10.1109/ReCoSoC.2016.7533909},
Howpublished = {16-45 BOG16 ReCoSoC},
Booktitle = {<em>In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</em>},
Abstract = {Optical on-chip communication technology provides an unprecedented bandwidth. It allows to connect the hundreds or even thousands of processing elements expected in many core systems using optical Network-on-Chip. However, the required buffers to interface the electrical and optical layers are very large, since optical data-flow cannot be stored. Moreover, on-chip optical technologies have high defect rates which limits its usability severely. In order to address these challenges, this work presents a buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition. The buffer-efficiency is achieved by a global credit-based arbitration with optical tokens. Further on, the architecture autonomously detects permanent errors in the optical components and configures the communication paths to avoid them. The work provides a thorough analysis at the gate-level of the area overhead incurred by the electrical sub-modules of the proposed system. It shows the practicability of the approach, experimental validated on a FPGA prototype. Compared with previously reported optical networks, it achieves an area reduction of up to 80% with almost identical performance.}
}

@inproceedings{GRBZFTH15,
Author = {Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener and J&uuml;rgen Teich},
Title = {A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering.},
Year = {(2015).},
Month = {December},
Note = {dziener, ESD},
Address = {Queenstown / New Zealand},
Isbn = {10.1109/FPT.2015.7393148},
Howpublished = {15-20 GRBZFTH15 FPT},
Booktitle = {<em>In Proceedings of the International Conference on Field-Programmable Technology (FPT)</em>},
Abstract = {In this paper, we present a novel architecture for high throughput database query processing. This architecture is based on an intelligent hardware/software co-design and consists of a highly configurable FPGA-based filter chain with arithmetic operation support and an alignment unit. It feeds the filtered data directly and in a cache-optimized way to an embedded processor which are responsible for joining tables and post processing. High throughput interfaces and parallelism of FPGAs are thus combined in order to provide reduced and cache-aligned data for optimized processor access. As a key component, we introduce a new highly configurable bloom filter cascade to relieve a processor of time-consuming hash-value computation and to significantly reduce the data for hash joins. It is shown that this unique approach may reduce the amount of data to be processed by the processors in typical data-warehouse applications by several orders of magnitude. The proposed architecture has been implemented on the embedded low-energy system-on-chip (SoC) platform Xilinx Zynq. Performance results for standard benchmarks show an up to 10~x higher throughput compared to a full featured x86-based processor at only a fraction of energy consumption.}
}

@inproceedings{BEZT15,
Author = {Andreas Becher, Jorge Echavarria, Daniel Ziener and J&uuml;rgen Teich},
Title = {Approximate Adder Structures on FPGAs.},
Year = {(2015).},
Month = {October},
Note = {dziener, ESD},
Address = {Paderborn / Germany},
Howpublished = {15-30 BEZT15 AC},
Booktitle = {<em>In Proceedings of the Workshop on Approximate Computing (AC)</em>},
Abstract = {In this paper, we propose novel approximate adder structures for FPGA-based implementations. These adder structures take advantage of the available FPGA resources. Compared with a full featured accurate adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structures, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.}
}

@inproceedings{LuFa15b,
Author = {Arno Luppold and Heiko Falk},
Title = {Schedulability aware WCET-Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems.},
Year = {(2015).},
Pages = {101-104},
Month = {June},
Note = {aluppold, hfalk, ESD, emp2, tacle, WCC},
Series = {20150601-scopes-luppold.pdf},
Address = {St. Goar / Germany},
Isbn = {10.1145/2764967.2771930},
Howpublished = {15-70 LuFa15b SCOPES},
Booktitle = {<em>In Proceedings of the 18th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {In hard real-time multitasking systems, applying WCET-oriented code optimizations to individual tasks may not lead to optimal results with regard to the system's schedulability. We propose an approach based on Integer-Linear Programming which is able to perform schedulability aware code optimizations for periodic task sets with fixed priorities. We evaluate our approach by using a static instruction SPM optimization for the Infineon TriCore microcontroller.}
}

@inproceedings{LuFa15a,
Author = {Arno Luppold and Heiko Falk},
Title = {Code Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems.},
Year = {(2015).},
Pages = {35-42},
Month = {April},
Note = {aluppold, hfalk, ESD, emp2, tacle, WCC},
Series = {20150416-isorc-luppold.pdf},
Address = {Auckland / New Zealand},
Isbn = {10.1109/ISORC.2015.8},
Howpublished = {15-80 LuFa15a ISORC},
Booktitle = {<em>In Proceedings of the 18th International Symposium on Real-Time Distributed Computing (ISORC)</em>},
Abstract = {In hard real-time systems, each task has to provably finish its execution within its respective deadline. Compiler optimizations can be used to improve each task's timing behavior. However, current compilers do not consider tasks' deadlines and can therefore not be used to reliably optimize hard real-time systems with regard to its schedulability. We propose a compiler optimization framework based on Integer-Linear Programming which allows for schedulability aware code optimizations of hard real-time multitasking systems. We evaluate the framework using an instruction scratchpad optimization. The results show that our approach can be used to improve the schedulability of hard real-time systems significantly.}
}

@article{CCK+15,
Author = {Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo and Heiko Falk},
Title = {Real-Time Task Scheduling on Island-Based Multi-Core Platforms.},
Journal = {<em>IEEE Transactions on Parallel and Distributed Systems (TPDS)</em>.},
Year = {(2015).},
Volume = {<strong>26</strong>.},
Number = {(2),},
Pages = {538-550},
Month = {February},
Note = {hfalk, ESD, emp2, tacle},
Publisher = {IEEE:},
Isbn = {10.1109/TPDS.2013.2297308},
Howpublished = {15-90 CCK+15 TPDS},
Abstract = {With the increasing number of cores in a computing system, how to coordinate the computing units and heterogeneous memory resources has soon become extremely critical for real-time systems. This paper explores the joint considerations of memory management and real-time task scheduling over island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. The objective of this work is to minimize the number of needed islands to successfully schedule real-time tasks. When the required amount of the local memory space is specified for each task, a scheduling algorithm is proposed to provide an asymptotic 29/9-approximation bound. When there is flexibility in determining the needed local memory space for each task, we propose an algorithm with an asymptotic 4-approximation bound to jointly manage memory resources and allocate computing cores. In addition to the worst-case approximation analysis, the proposed algorithms are also evaluated with 82 real-life benchmarks with the support of a worst-case execution time analyzer. Moreover, extensive evaluations are conducted to show the capability of the proposed approaches when being used with various computing cores and memory resources.}
}

@unpublished{EF:2015,
Author = {Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers)},
Title = {Workshop on Design Automation for Understanding Hardware Designs (DUHDe).},
Year = {(2015).},
Note = {gfey, CE},
Howpublished = {15-999 EF:2015}
}

@inproceedings{AF:2015,
Author = {Gökçe Aydos and Goerschwin Fey},
Title = {Empirical Results on Parity-based Soft Error Detection with Software-based Retry.},
Year = {(2015).},
Note = {gfey, CE},
Howpublished = {15-999 AF:2015 NORCAS},
Booktitle = {<em>IEEE Nordic Circuits and Systems Conference (NORCAS)</em>}
}

@inproceedings{RKF:2015,
Author = {Heinz Riener and Michael Kirkedal Thomsen and Goerschwin Fey},
Title = {Execution Tracing of C Code for Formal Analysis (Extended Abstract).},
Year = {(2015).},
Pages = {160-164},
Note = {gfey, CE},
Howpublished = {15-999 RKF:2015 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{REF:2015,
Author = {Heinz Riener and Rüdiger Ehlers and Goerschwin Fey},
Title = {Path-Based Program Repair.},
Year = {(2015).},
Pages = {22-32},
Note = {gfey, CE},
Howpublished = {15-999 REF:2015 FESCA},
Booktitle = {<em>International Workshop on Formal Engineering approaches to Software Components and Architectures (FESCA), Satellite event of ETAPS</em>}
}

@inproceedings{MMZF:2015,
Author = {Jabier Martinez and Jan Malburg and Tewfik Ziadi and Goerschwin Fey},
Title = {Towards analysing feature locations through testing traces with BUT4Reuse.},
Year = {(2015).},
Pages = {10-15},
Note = {gfey, CE},
Howpublished = {15-999 MMZF:2015 DUHDE},
Booktitle = {<em>Workshop on Design Automation for Understanding Hardware Designs (DUHDe)</em>}
}

@book{Zimm15,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2015).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20150722-computability-theory-zimmermann.pdf},
Edition = {5.},
Isbn = {10.15480/882.1247},
Howpublished = {15-50 Zimm15 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year Bachelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to present the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg.<br /> In the second edition, 2012, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complemented by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each problem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-known result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch. In the fourth and fifth editions, some small amendments have been make.}
}

@article{DF:2015,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Transaction-based online debug for NoC-based multiprocessor SoCs.},
Journal = {<em>Microprocessors and Microsystems (MICPRO)</em>.},
Year = {(2015).},
Pages = {157-166},
Note = {gfey, CE},
Isbn = {http://dx.doi.org/10.1016/j.micpro.2015.03.003},
Howpublished = {15-999 DF:2015 MICPRO}
}

@book{DF:2014e,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Debug Automation from Pre-Silicon to Post-Silicon.},
Year = {(2015).},
Pages = {171},
Note = {gfey, CE},
Howpublished = {15-999 DF:2014e}
}

@inproceedings{TFG:2015,
Author = {Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz},
Title = {Conservatively Analyzing Transient Faults.},
Year = {(2015).},
Pages = {50-55},
Note = {gfey, CE},
Howpublished = {15-999 TFG:2015 ISVLSI},
Booktitle = {<em>IEEE Annual Symposium on VLSI (ISVLSI)</em>}
}

@inproceedings{TFG:2015b,
Author = {Niels Thole and Goerschwin Fey and Alberto Garcia-Ortiz},
Title = {Analyzing an SET at Gate Level using a Conservative Approach.},
Year = {(2015).},
Note = {gfey, CE},
Howpublished = {15-999 TFG:2015b TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{TRF:2015,
Author = {Niels Thole and Heinz Riener and Fey, Goerschwin},
Title = {Equivalence Checking on System Level using A Priori Knowledge.},
Year = {(2015).},
Pages = {177-182},
Note = {gfey, CE},
Howpublished = {15-999 TRF:2015 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{FSF:2015,
Author = {Tino Flenker and André Sülflow and Goerschwin Fey},
Title = {Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation.},
Year = {(2015).},
Pages = {145-150},
Note = {gfey, CE},
Howpublished = {15-999 FSF:2015 ATS},
Booktitle = {<em>Asian Test Symposium (ATS)</em>}
}

@proceedings{YA+:2015,
Author = {Trond Ytterdal and Snorre Aunet and General Chairs and Bjørn B. Larsen and Görschwin Fey (editors)},
Title = {22nd European conference on circuit theory and design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015.},
Year = {(2015).},
Note = {gfey, CE},
Howpublished = {15-999 YA+:2015 ECCTD},
Booktitle = {<em>European Conference on Circuit Theory and Design (ECCTD)</em>}
}

@article{FSF:2014,
Author = {Alexander Finder and André Sülflow and Goerschwin Fey},
Title = {Latency Analysis for Sequential Circuits.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2014).},
Pages = {643-647},
Note = {gfey, CE},
Isbn = {10.1109/TCAD.2013.2292501},
Howpublished = {14-999 FSF:2014 TCAD}
}

@inproceedings{LuFa14,
Author = {Arno Luppold and Heiko Falk},
Title = {Schedulability-Oriented WCET-Optimization of Hard Real-Time Multitasking Systems.},
Year = {(2014).},
Pages = {9-12},
Month = {October},
Note = {aluppold, hfalk, ESD, emp2, tacle, WCC},
Series = {20141008-jrwrtc-luppold.pdf},
Address = {Versailles / France},
Howpublished = {14-10 LuFa14 JRWRTC},
Booktitle = {<em>In Proceedings of the 8th Junior Researcher Workshop on Real-Time Computing (JRWRTC)</em>},
Abstract = {In multitasking hard real-time systems, each task's response time must provably be lower than or equal to its deadline. If the system does not hold all timing constraints, WCET-oriented optimizing compilers can be used to improve each task's worst-case runtime behaviour. However, current optimizations do not account for a system's schedulability constraints. We provide an approach based on Integer-Linear Programming (ILP) for schedulability-oriented WCET optimization of hard real-time systems.}
}

@inproceedings{TSG+:2014,
Author = {Carl Johann Treudler and Jan-Carsten Schröder and Fabian Greif and Kai Stohlmann and Gökçe Aydos and Goerschwin Fey},
Title = {Scalability of a Base Level Design for an On-Board-Computer for Scientific Missions.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 TSG+:2014 DASIA},
Booktitle = {<em>Data Systems In Aerospace (DASIA)</em>}
}

@inproceedings{LWS+:2014,
Author = {Daniel Lüdtke and Karsten Westerdorff and Kai Stohlmann and Anko Börner and Olaf Maibaum and Ting Peng and Benjamin Weps and Goerschwin Fey and Andreas Gerndt},
Title = {OBC-NG: Towards a Reconfigurable On-board Computing Architecture for Spacecraft.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 LWS+:2014 AEROCONF},
Booktitle = {<em>IEEE Aerospace Conference (AEROCONF)</em>}
}

@unpublished{EF:2014,
Author = {Emmanuelle Encrenaz-Tiphene and Goerschwin Fey (Organizers)},
Title = {Workshop on Design Automation for Understanding Hardware Designs (DUHDe).},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 EF:2014}
}

@inproceedings{Fey:2014,
Author = {Goerschwin Fey},
Title = {Command and Data Handling Infrastructure for Space Systems (Invited Talk).},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 Fey:2014 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@misc{Falk14a,
Author = {Heiko Falk},
Title = {WCET-aware compilation and optimization.},
Year = {(2014).},
Month = {June},
Note = {hfalk, ESD, tacle, WCC},
Series = {20140627-tacle-summerschool-falk.pdf},
Address = {Venice / Italy},
Howpublished = {14-50 Falk14a TACLe},
Type = {Lecture at the TACLe Summer School,}
}

@proceedings{Falk14b,
Author = {Heiko Falk (Ed.)},
Title = {Proceedings of the 14th International Workshop on Worst-Case Execution Time Analysis (WCET).},
Year = {(2014).},
Month = {July},
Note = {hfalk, ESD, tacle},
Address = {Madrid / Spain},
Isbn = {10.4230/OASIcs.WCET.2014.i},
Howpublished = {14-45 Falk14b WCET},
Url = {http://www.uni-ulm.de/wcet2014}
}

@inproceedings{RSW+:2014,
Author = {Heinz Riener and Mathias Soeken and Clemens Werther and Goerschwin Fey and Rolf Drechsler},
Title = {metaSMT: A Unified Interface to SMT-LIB2.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 RSW+:2014 FDL},
Booktitle = {<em>Forum on Specification and Design Languages (FDL)</em>}
}

@inproceedings{RKDF:2014,
Author = {Heinz Riener and Oliver Keszocze and Rolf Drechsler and Goerschwin Fey},
Title = {A Logic for Cardinality Constraints (Extended Abstract).},
Year = {(2014).},
Pages = {217-220},
Note = {gfey, CE},
Howpublished = {14-999 RKDF:2014 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@article{MFF:2014,
Author = {Jan Malburg and Alexander Finder and Goerschwin Fey},
Title = {A Simulation Based Approach for Automated Feature Localization.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2014).},
Pages = {1886-1899},
Note = {gfey, CE},
Isbn = {10.1109/TCAD.2014.2360462},
Howpublished = {14-999 MFF:2014 TCAD}
}

@inproceedings{MEF:2014,
Author = {Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey},
Title = {Mutation based Feature Localization.},
Year = {(2014).},
Pages = {49-54},
Note = {gfey, CE},
Howpublished = {14-999 MEF:2014 MTV},
Booktitle = {<em>International Workshop on Microprocessor Test and Verification (MTV)</em>}
}

@inproceedings{MEF:2014b,
Author = {Jan Malburg and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey},
Title = {Mutation based Feature Localization.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 MEF:2014b DUHDE},
Booktitle = {<em>Workshop on Design Automation for Understanding Hardware Designs (DUHDe)</em>}
}

@inproceedings{MKF:2014,
Author = {Jan Malburg and Niklas Krafczyk and Goerschwin Fey},
Title = {Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 MKF:2014 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{BFL:2014,
Author = {Kai Borchers and Goerschwin Fey and Daniel Luedtke},
Title = {Automatic Performance Tracking of a SpaceWire Network.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 BFL:2014 SPW},
Booktitle = {<em>International SpaceWire Conference</em>}
}

@book{Zimm14,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2014).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20140702-computability-theory-zimmermann.pdf},
Edition = {4.},
Isbn = {10.15480/882.1177},
Howpublished = {14-40 Zimm14 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year Bachelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to present the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg.<br /> In the second edition, 2012, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complemented by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each problem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-known result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch. In the fourth edition, some small amendments have been make.}
}

@inproceedings{DF:2014f,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 DF:2014f TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{DF:2014d,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {SAT-Based Speedpath Debugging Using Waveforms.},
Year = {(2014).},
Pages = {63-68},
Note = {gfey, CE},
Howpublished = {14-999 DF:2014d ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@inproceedings{DF:2014c,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs.},
Year = {(2014).},
Pages = {400-404},
Note = {gfey, CE},
Isbn = {10.1109/PDP.2014.72},
Howpublished = {14-999 DF:2014c PDP},
Booktitle = {<em>Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP)</em>}
}

@inproceedings{DF:2014b,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Debug Automation for Synchronization Bugs at RTL.},
Year = {(2014).},
Pages = {44-49},
Note = {gfey, CE},
Isbn = {10.1109/VLSID.2014.15},
Howpublished = {14-999 DF:2014b VLSIDC},
Booktitle = {<em>VLSI Design Conference</em>}
}

@phdthesis{Hanif14,
Author = {Muhammad Kashif Hanif},
Title = {Mapping Dynamic Programming Algorithms on Graphics Processing Units.},
Year = {(2014).},
Month = {July},
Note = {AEG},
Series = {20140703-phdthesis-hanif.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.1184},
Howpublished = {14-30 Hanif14 PhD},
Type = {Ph.D. Thesis.},
School = {Hamburg University of Technology},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {The Graphics Processing Unit (GPU) is a highly parallel, many-core streaming architecture that can execute hundreds of threads concurrently. The data parallel architecture of the GPU is suitable to perform computation intensive applications. In recent years, the use of GPUs for general purpose computation has increased and a large set of problems can be tackled by mapping onto GPUs. The programming model CUDA enables to design C like programs with some extensions which leverages programmers to efficiently use the graphics API.<br /> Alignment is the fundamental operation used to compare biological sequences and in this way to identify regions of similarity that are eventually consequences of structural, functional, or evolutionary relationships. Multiple sequence alignment is an important tool for the simultaneous alignment of three or more sequences. Efficient heuristics exist to cope with this problem.<br /> In the thesis, progressive alignment methods and their parallel implementation by GPUs are studied. More specifically, the dynamic programming algorithms of profile-profile and profile-sequence alignment are mapped onto GPU. Wavefront and matrix-matrix product techniques are discussed which can deal well with the data dependencies. The performance of these methods is analyzed. Simulations show that one order of magnitude of speed-up over the serial version can be achieved.<br /> ClustalW is the most widely used progressive sequence alignment method which aligns more closely related sequences first and then gradually adds more divergent sequences. It consists of three stages: distance matrix calculation, guide tree compilation, and progressive alignment. In this work, the efficient mapping of the alignment stage onto GPU by using a combination of wavefront and matrix-matrix product techniques has been studied.<br /> In the hidden Markov model, the Viterbi algorithm is used to find the most probable sequence of hidden states that has generated the observation. In the thesis, the parallelism exhibited by the compute intensive tasks is studied and a parallel solution based on the matrix-matrix product method onto GPU is devised. Moreover, the opportunity to use optimized BLAS library provided by CUDA is explored. Finally, the performance by fixing the number of states and changing the number of observations and vice versa is portrayed.<br /> At the end, general principles and guidelines for GPU programming of matrix-matrix product algorithms are discussed.}
}

@article{DuZi14b,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Gr&ouml;bner bases for perfect binary codes.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2014).},
Volume = {<strong>91</strong>.},
Number = {(2),},
Pages = {155-167},
Month = {February},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20140225-dueck-ijpam.pdf},
Isbn = {10.12732/ijpam.v91i2.2},
Howpublished = {14-85 DuZi14b IJPAM},
Abstract = {There is a deep connection between linear codes and combinatorial designs. Combinatorial designs can give rise to linear codes and vice versa. In particular, perfect codes always hold combinatorial designs. Recently, linear codes have been associated to binomial ideals by the so-called code ideal which completely describes the code. It will be shown that for a perfect binary linear code, the codewords of minimum Hamming weight are in one-to-one correspondence with the elements of a reduced Gr&ouml;bner basis for the code ideal with respect to any graded order.}
}

@article{DuZi14a,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Singleton codes.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2014).},
Volume = {<strong>91</strong>.},
Number = {(3),},
Pages = {273-290},
Month = {January},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {201401-dueck-ijpam.pdf},
Isbn = {10.12732/ijpam.v91i3.1},
Howpublished = {14-95 DuZi14a IJPAM},
Abstract = {Each linear code can be described by a so-called code ideal. In order to utilize this ideal, Gr&ouml;bner bases are required. Since many results depend on the chosen term order, knowledge of the universal Gr&ouml;bner basis is advantageous. Singleton codes have the property that the universal Gr&ouml;bner basis for their code ideals consists of all binomials associated to a codeword whose Hamming weight satisfies the Singleton bound. In this paper, properties of Singleton codes will be established and it will be examined which classical binary linear codes belong to the class of Singleton codes.}
}

@article{DuZi14d,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Heuristic decoding of linear codes using commutative algebra.},
Journal = {<em>Designs, Codes and Cryptography (DCC)</em>.},
Year = {(2014).},
Volume = {<strong>76</strong>.},
Number = {(1),},
Pages = {23-35},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/s10623-014-0008-8},
Howpublished = {14-35 DuZi14d DCC},
Abstract = {Each binary linear code can be associated to a binomial ideal which allows for a complete decoding. Two generalizations of the non-binary case given by the ordinary and generalized code ideals have been given which coincide in the binary case and are related by elimination. The approach based on the generalized code ideal provides complete decoding but can be rather cumbersome. In this paper, a new heuristic decoding method based on the ordinary code ideal will be given which can be much faster.}
}

@article{DuZi14c,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Vector space bases for the homogeneous parts in homogeneous ideals and graded modules over a polynomial ring.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2014).},
Volume = {<strong>93</strong>.},
Number = {(6),},
Pages = {835-844},
Month = {June},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20140617-dueck-ijpam.pdf},
Isbn = {10.12732/ijpam.v93i6.9},
Howpublished = {14-55 DuZi14c IJPAM},
Abstract = {In this paper, vector space bases for the homogeneous parts of homogeneous ideals and graded modules over a commutative polynomial ring are given using Gr&ouml;bner bases.}
}

@inproceedings{RLF14,
Author = {Nicolas Roeser, Arno Luppold and Heiko Falk},
Title = {Multi-Criteria Optimization of Hard Real-Time Systems.},
Year = {(2014).},
Pages = {49-52},
Month = {October},
Note = {aluppold, hfalk, ESD, tacle},
Series = {20141008-jrwrtc-roeser.pdf},
Address = {Versailles / France},
Howpublished = {14-05 RLF14 JRWRTC},
Booktitle = {<em>In Proceedings of the 8th Junior Researcher Workshop on Real-Time Computing (JRWRTC)</em>},
Abstract = {Modern embedded hard real-time systems often have to comply with several design constraints. On the one hand, the system's execution time has to be provably less than or equal to a given deadline. On the other hand, further constraints may be given with regard to maximum code size and energy consumption due to limited resources. We propose an idea for a compiler-based approach to automatically optimize embedded hard real-time systems with regard to multiple optimization criteria.}
}

@inproceedings{TF:2014,
Author = {Niels Thole and Goerschwin Fey},
Title = {Equivalence Checking on System Level using Stepwise Induction.},
Year = {(2014).},
Pages = {197-200},
Note = {gfey, CE},
Howpublished = {14-999 TF:2014 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@article{AEF+14,
Author = {Philip Axer, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan, Bengt Jonsson, Peter Marwedel, Jan Reineke, Christine Rochange, Maurice Sebastian, Reinhard von Hanxleden, Reinhard Wilhelm and Wang Yi},
Title = {Building Timing Predictable Embedded&nbsp;Systems.},
Journal = {<em>ACM Transactions on Embedded Computing Systems (TECS)</em>.},
Year = {(2014).},
Volume = {<strong>13</strong>.},
Number = {(4),},
Month = {February},
Note = {hfalk, ESD, tacle, WCC},
Publisher = {ACM:},
Series = {20140210-acm-tecs-axer.pdf},
Isbn = {10.1145/2560033},
Howpublished = {14-80 AEF+14 TECS},
Type = {&copy; ACM, 2014. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published},
Abstract = {A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.}
}

@book{EFP:2014,
Author = {Stephan Eggersglüß and Goerschwin Fey and Ilia Polian},
Title = {Test digitaler Schaltkreise.},
Year = {(2014).},
Note = {gfey, CE},
Howpublished = {14-999 EFP:2014}
}

@article{CCR+14,
Author = {Sudipta Chattopadhyay, Lee Kee Chong, Abhik Roychoudhury, Timon Kelter, Peter Marwedel and Heiko Falk},
Title = {A Unified WCET Analysis Framework for Multicore Platforms.},
Journal = {<em>ACM Transactions on Embedded Computing Systems (TECS)</em>.},
Year = {(2014).},
Volume = {<strong>13</strong>.},
Number = {(4s),},
Month = {July},
Note = {hfalk, ESD, emp2, tacle, WCC},
Publisher = {ACM:},
Series = {20140710-acm-tecs-chattopadhyay.pdf},
Isbn = {10.1145/2584654},
Howpublished = {14-25 CCR+14 TECS},
Type = {&copy; ACM, 2014. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published},
Abstract = {With the advent of multicore architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.}
}

@article{KFM+14,
Author = {Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury},
Title = {Static analysis of multi-core TDMA resource arbitration delays.},
Journal = {<em>the International Journal of Time-Critical Computing Systems (Real-Time Systems)</em>.},
Year = {(2014).},
Volume = {<strong>50</strong>.},
Number = {(2),},
Pages = {185-229},
Month = {March},
Note = {hfalk, ESD, emp2, tacle, WCC},
Publisher = {Springer:},
Series = {20140311-springer-rts-kelter.pdf},
Isbn = {10.1007/s11241-013-9189-x},
Howpublished = {14-70 KFM+14 RTS},
Abstract = {In the development of hard real-time systems, knowledge of the Worst-Case Execution Time (WCET) is needed to guarantee the safety of a system. For single-core systems, static analyses have been developed which are able to derive guaranteed bounds on a program's WCET. Unfortunately, these analyses cannot directly be applied to multi-core scenarios, where the different cores may interfere with each other during the access to shared resources like for example shared buses or memories. For the arbitration of such resources, TDMA arbitration has been shown to exhibit favorable timing predictability properties. In this article, we review and extend a methodology for analyzing access delays for TDMA-arbitrated resources. Formal proofs of the correctness of these methods are given and a thorough experimental evaluation is carried out, where the presented techniques are compared to preexisting ones on an extensive set of real-world benchmarks for different classes of analyzed systems.}
}

@inproceedings{FWF:2013,
Author = {Alexander Finder and Jan-Philipp Witte and Goerschwin Fey},
Title = {Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications.},
Year = {(2013).},
Pages = {60-65},
Note = {gfey, CE},
Howpublished = {13-999 FWF:2013 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@article{LMFS13b,
Author = {Arno Luppold, Benjamin Menhorn, Heiko Falk and Frank Slomka},
Title = {A New Concept for System-Level Design of Runtime Reconfigurable Real-Time&nbsp;Systems.},
Journal = {<em>the ACM SIGBED Review</em>.},
Year = {(2013).},
Volume = {<strong>10</strong>.},
Number = {(4),},
Pages = {57-60},
Month = {December},
Note = {aluppold, hfalk, ESD},
Publisher = {ACM:},
Series = {201312-acm-sigbed-review-luppold.pdf},
Isbn = {10.1145/2583687.2583701},
Howpublished = {13-45 LMFS13b SIGBED},
Abstract = {This concept paper proposes a new system-level design methodology for runtime reconfigurable adaptive heterogeneous systems in a real-time environment. Today, among those approaches dealing with runtime reconfiguration and hardware/software co-design, compliance with hard real-time conditions is not guaranteed. Our approach will fill this gap. In contrast to other approaches, we apply methods of real-time analysis to embedded reconfigurable systems. An extended compiler and a runtime resource manager guarantee both synthesis and reconfiguration in a (hard) real-time environment. With this approach, the system can adapt to changes in requirements and operational environments during runtime.}
}

@inproceedings{LMFS13a,
Author = {Arno Luppold, Benjamin Menhorn, Heiko Falk and Frank Slomka},
Title = {A New Concept for System-Level Design of Runtime Reconfigurable Real-Time Systems.},
Year = {(2013).},
Month = {April},
Note = {aluppold, hfalk, ESD},
Series = {20130408-apres-luppold-menhorn.pdf},
Address = {Philadelphia / USA},
Howpublished = {13-85 LMFS13a APRES},
Booktitle = {<em>In Proceedings of the 5th Workshop on Adaptive and Reconfigurable Embedded Systems (APRES)</em>},
Abstract = {This concept paper proposes a new system-level design methodology for runtime reconfigurable adaptive heterogeneous systems in a real-time environment. Today, among those approaches dealing with runtime reconfiguration and hardware/software co-design, compliance with hard real-time conditions is not guaranteed. Our approach will fill this gap. In contrast to other approaches, we apply methods of real-time analysis to embedded reconfigurable systems. An extended compiler and a runtime resource manager guarantee both synthesis and reconfiguration in a (hard) real-time environment. With this approach, the system can adapt to changes in requirements and operational environments during runtime.}
}

@inproceedings{CCK+13,
Author = {Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo and Heiko Falk},
Title = {Real-Time Partitioned Scheduling on Multi-Core Systems with Local and Global Memories.},
Year = {(2013).},
Pages = {467-472},
Month = {January},
Note = {hfalk, ESD, emp2, tacle},
Series = {20130124-aspdac-chang.pdf},
Address = {Yokohama / Japan},
Isbn = {10.1109/ASPDAC.2013.6509640},
Howpublished = {13-95 CCK+13 ASP-DAC},
Booktitle = {<em>In Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC)</em>},
Abstract = {Real-time task scheduling becomes even more challenging with the emerging of island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. With such a popular architecture design in mind, this paper exploits real-time task scheduling over island-based homogeneous cores with local and global memory pools. Joint considerations of real-time scheduling and memory allocation are presented to efficiently use the computing and memory resources. A polynomial-time algorithm with an asymptotic 4-approximation bound is proposed to minimize the number of needed islands to successfully schedule tasks. To evaluate the performance of the proposed algorithm, 82 benchmarks from the MRTC, MediaBench, UTDSP, NetBench, and DSPstone benchmark suites were profiled by a worst-case-execution-time analyzer aiT and included in the experiments.}
}

@article{GFD:2013,
Author = {Daniel Grosse and Goerschwin Fey and Rolf Drechsler},
Title = {Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis.},
Journal = {<em>Electronic Communications of the EASST</em>.},
Year = {(2013).},
Pages = {13 pages},
Note = {gfey, CE},
Isbn = {10.14279/tuj.eceasst.62.860.854},
Howpublished = {13-999 GFD:2013 ECEASST}
}

@unpublished{FS:2013,
Author = {Goerschwin Fey and Matteo Sonza Reorda (Organizers)},
Title = {Reliability Analysis Reloaded: How Will We Survive? (Embedded Tutorial).},
Year = {(2013).},
Note = {gfey, CE},
Howpublished = {13-999 FS:2013 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{RF:2013c,
Author = {Heinz Riener and Goerschwin Fey},
Title = {Yet a Better Error Explanation Algorithm (Extended Abstract).},
Year = {(2013).},
Pages = {193-194},
Note = {gfey, CE},
Howpublished = {13-999 RF:2013c MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{RFF:2013,
Author = {Heinz Riener and Stefan Frehse and Goerschwin Fey},
Title = {Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis.},
Year = {(2013).},
Pages = {939-942},
Note = {gfey, CE},
Howpublished = {13-999 RFF:2013 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{KFM13,
Author = {Jan C. Kleinsorge, Heiko Falk and Peter Marwedel},
Title = {Simple Analysis of Partial Worst-case Execution Paths on General Control Flow Graphs.},
Year = {(2013).},
Month = {October},
Note = {hfalk, ESD, emp2, tacle, WCC},
Series = {20131001-emsoft-kleinsorge.pdf},
Address = {Montreal / Canada},
Isbn = {10.1109/EMSOFT.2013.6658594},
Howpublished = {13-50 KFM13 EMSOFT},
Booktitle = {<em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em>},
Abstract = {One of the most important computations in static worst-case execution time analyses is the path analysis which computes the potentially most time-consuming execution path in a program. This is typically done either with an implicit path computation based on solving an integer linear program, or with explicit path computations directly on the program's control flow graph. The former approach is powerful and comparably simple to use but hard to extend and to combine with other program analyses due to its restriction to the linear equation model. The latter approaches are often restricted to well-structured graphs, suffer from inaccuracy or require non-trivial structural analyses or graph transformations upfront or during their computations.<br /> In this paper, we propose a generalized computational model and a comprehensive explicit path analysis that operates on arbitrary directed control flow graphs. We propose simple and yet effective techniques to deal with unstructured control flows and complex flow fact models. The analysis does not require a control flow graph to be mutable, is non-recursive, fast, and provides the means to compute all worst-case paths from arbitrary source nodes. It is well suited for solving local problems and the computation of partial solutions, which is highly relevant for problems related to scheduling and execution modes alike.}
}

@inproceedings{MFF:2013b,
Author = {Jan Malburg and Alexander Finder and Goerschwin Fey},
Title = {Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns.},
Year = {(2013).},
Pages = {59-66},
Note = {gfey, CE},
Howpublished = {13-999 MFF:2013b ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@inproceedings{MFF:2013,
Author = {Jan Malburg and Alexander Finder and Goerschwin Fey},
Title = {Tuning Dynamic Data Flow Analysis to Support Design Understanding.},
Year = {(2013).},
Pages = {1179-1184},
Note = {gfey, CE},
Howpublished = {13-999 MFF:2013 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@book{Zimm13,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2013).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20130723-computability-theory-zimmermann.pdf},
Edition = {3.},
Isbn = {10.15480/882.1121},
Howpublished = {13-60 Zimm13 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year Bachelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to present the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg.<br /> In the second edition, 2012, minor changes were made. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added. In the third edition, 2013, the eight chapters on computability theory were complemented by a short introduction to computational complexity theory. The added chapter provides a brief presentation of the central open question in complexity theory which is one of the millenium price problems in mathematics asking roughly whether each problem whose solution can be verified in polynomial time can also be solved in polynomial time. The chapter includes the well-known result of Stephen Cook and Leonid Lewin that the satisfiabilty problem is NP-complete and also its proof from scratch.}
}

@proceedings{SF+:2013,
Author = {Lukáŝ Sekanina and Görschwin Fey and Jaan Raik and Snorre Aunet and Richard Ruzicka (editors)},
Title = {16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013.},
Year = {(2013).},
Note = {gfey, CE},
Howpublished = {13-999 SF+:2013 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@article{DSF:2013,
Author = {Mehdi Dehbashi and André Sülflow and Goerschwin Fey},
Title = {Automated Design Debugging in a Testbench-Based Verification Environment.},
Journal = {<em>Microprocessors and Microsystems (MICPRO)</em>.},
Year = {(2013).},
Pages = {206-217},
Note = {gfey, CE},
Howpublished = {13-999 DSF:2013 MICPRO}
}

@article{DF:2013,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Debug Automation for Logic Circuits Under Timing Variations.},
Journal = {<em>IEEE Design and Test of Computers (DT)</em>.},
Year = {(2013).},
Pages = {60-69},
Note = {gfey, CE},
Isbn = {10.1109/MDAT.2013.2266393},
Howpublished = {13-999 DF:2013 DT}
}

@inproceedings{DF:2013c,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Efficient Automated Speedpath Debugging.},
Year = {(2013).},
Pages = {48-53},
Note = {gfey, CE},
Howpublished = {13-999 DF:2013c DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{DF:2013e,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Towards Debug Automation for Timing Bugs at RTL.},
Year = {(2013).},
Note = {gfey, CE},
Howpublished = {13-999 DF:2013e TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@article{DuZi13b,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Universal Gr&ouml;bner bases for linear codes.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2013).},
Volume = {<strong>86</strong>.},
Number = {(2),},
Pages = {345-358},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20130719-dueck-ijpam.pdf},
Isbn = {10.12732/ijpam.v86i2.9},
Howpublished = {13-65 DuZi13b IJPAM},
Abstract = {Each linear code can be described by a code ideal given as the sum of a toric ideal and a non-prime ideal. In this way, several concepts from the theory of toric ideals can be translated into the setting of code ideals. It will be shown that after adjusting some of these concepts, the same inclusion relationship between the set of circuits, the universal Gr&ouml;bner basis and the Graver basis holds. Furthermore, in the case of binary linear codes, the universal Gr&ouml;bner basis will consist of all binomials which correspond to codewords that satisfy the Singleton bound and a particular rank condition. This will give rise to a new class of binary linear codes denoted as Singleton codes.}
}

@article{DuZi13a,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Computing generating sets for quaternary codes using Gr&ouml;bner bases.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2013).},
Volume = {<strong>84</strong>.},
Number = {(1),},
Pages = {99-109},
Month = {April},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20130402-dueck-ijpam.pdf},
Isbn = {10.12732/ijpam.v84i1.7},
Howpublished = {13-90 DuZi13a IJPAM},
Abstract = {Gr&ouml;bner bases techniques can be used to compute a basis of a subspace of a finite-dimensional vector space over finite prime field given as a matrix kernel. Linear codes can be described as such subspaces and thus are an interesting area of application. Based on this, Gr&ouml;bner bases techniques will be used to compute a generating set of a quaternary code given as a matrix kernel. In particular, if the quaternary code is free, the algorithm will provide a basis for the dual code.}
}

@inproceedings{AFK+:2013,
Author = {Rob Aitken and Goerschwin Fey and Zbigniew T. Kalbarczyk and Frank Reichenbach and Matteo Sonza Reorda},
Title = {Reliability Analysis Reloaded: How Will We Survive?.},
Year = {(2013).},
Pages = {358-367},
Note = {gfey, CE},
Howpublished = {13-999 AFK+:2013 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@article{ToZi13,
Author = {Svetlana Torgasin and Karl-Heinz Zimmermann},
Title = {An all-pairs shortest path algorithm for bipartite graphs.},
Journal = {<em>Central European Journal of Computer Science (CEJCS)</em>.},
Year = {(2013).},
Volume = {<strong>3</strong>.},
Number = {(4),},
Pages = {149-157},
Month = {December},
Note = {khzimmermann, AEG},
Publisher = {De Gruyter Open:},
Isbn = {10.2478/s13537-013-0110-4},
Howpublished = {13-40 ToZi13 CEJCS},
Abstract = {Bipartite graphs are widely used for modeling of complex structures in biology, engineering, and computer science. The search for shortest paths in such structures is a highly demanded procedure that requires optimization. This paper presents a variant of the all-pairs shortest path algorithm for bipartite graphs. The method is based on the distance matrix product and improves the general algorithm by exploiting the graph topology. The space complexity is reduced by a factor of at least four and the time complexity decreased by almost an order of magnitude when compared with the basic APSP algorithm.}
}

@inproceedings{KHMF13,
Author = {Timon Kelter, Tim Harde, Peter Marwedel and Heiko Falk},
Title = {Evaluation of resource arbitration methods for multi-core real-time systems.},
Year = {(2013).},
Pages = {1-10},
Month = {July},
Note = {hfalk, ESD, emp2, tacle, WCC},
Series = {20130709-wcet-kelter.pdf},
Address = {Paris / France},
Isbn = {10.4230/OASIcs.WCET.2013.1},
Howpublished = {13-70 KHMF13 WCET},
Booktitle = {<em>In Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {Multi-core systems have become prevalent in the last years, because of their favorable properties in terms of energy consumption, computing power and design complexity. First attempts have been made to devise WCET analyses for multi-core processors, which have to deal with the problem that the cores may experience interferences during accesses to shared resources. To limit these interferences, the vast amount of previous work is proposing a strict TDMA (time division multiple access) schedule for arbitrating shared resources. Though this type of arbitration yields a high predictability, this advantage is paid for with a poor resource utilization. In this work, we compare different arbitration methods with respect to their predictability and average case performance. We show how known WCET analysis techniques can be extended to work with the presented arbitration strategies and perform an evaluation of the resulting ACETs and WCETs on an extensive set of realworld benchmarks. Results show that there are cases when TDMA is not the best strategy, especially when predictability and performance are equally important.}
}

@phdthesis{Retter13,
Author = {Wolfram Retter},
Title = {Topics in Abstract Order Geometry.},
Year = {(2013).},
Month = {September},
Note = {AEG},
Series = {20130927-phdthesis-retter.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.1154},
Howpublished = {13-55 Retter13 PhD},
Type = {Ph.D. Thesis.},
School = {Hamburg University of Technology},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {An interval space is a set with a ternary relation satisfying some axioms that support the interpretation of the ternary relation as location of a point between two points. Some new concepts, including those of a topological, a quadrimodular and a quadrimedian interval space and a geodesic quadrimedian closure are developed. A sufficient criterion for embeddability of an interval space into a median metric space is proved. For two central structure theorems of analysis and algebra it is proved that analogues are valid for quadrimedian spaces, but do not hold in general for median spaces.}
}

@inproceedings{CCM+12,
Author = {Che-Wei Chang, Jian-Jia Chen, Waqaas Munawar, Tei-Wei Kuo and Heiko Falk},
Title = {Partitioned Scheduling for Real-Time Tasks on Multiprocessor Embedded Systems with Programmable Shared SRAMs.},
Year = {(2012).},
Pages = {153-162},
Month = {October},
Note = {hfalk, ESD, emp2, tacle},
Series = {20121008-emsoft-chang.pdf},
Address = {Tampere / Finland},
Isbn = {10.1145/2380356.2380384},
Howpublished = {12-25 CCM+12 EMSOFT},
Booktitle = {<em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em>},
Abstract = {This work is motivated by the advance of multiprocessor system architecture, in which the allocation of tasks over heterogeneous memory modules has a significant impact on the task execution. By considering two different types of memory modules with different access latencies, this paper explores joint considerations of memory allocation and real-time task scheduling to minimize the maximum utilization of processors of the system. For implicit-deadline sporadic tasks, a two-phase algorithm is developed, where the first phase determines memory allocation to derive a lower bound of the maximum utilization, and the second phase adopts worst-fit partitioning to assign tasks. It is shown that the proposed algorithm leads to a tight (2 - 2/(M+1))-approximation bound where M is the number of processors. The proposed algorithm is then evaluated with 82 realistic benchmarks from MRTC, MediaBench, UTDSP, NetBench and DSPstone, and extensive simulations are further conducted to analyze the proposed algorithm.}
}

@incollection{FF:2012,
Author = {Finder, Alexander and Fey, Görschwin},
Title = {Evaluating Debugging Algorithms from a Qualitative Perspective.},
Year = {(2012).},
Pages = {21-36},
Note = {gfey, CE},
Howpublished = {12-999 FF:2012 {SYSTEM SPECIFICATION AND DESIGN LANGUAGES -- SELECTED CONTRIBUTIONS FROM FDL 2010}},
Booktitle = {<em>System Specification and Design Languages - Selected Contributions from FDL 2010</em>}
}

@inproceedings{Fey:2012,
Author = {Goerschwin Fey},
Title = {Assessing System Vulnerability using Formal Verification Techniques.},
Year = {(2012).},
Pages = {47-56},
Note = {gfey, CE},
Howpublished = {12-999 Fey:2012 MEMICS_REV},
Booktitle = {<em>Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS) - Revised Selected Papers</em>}
}

@article{FFM+:2012,
Author = {Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (editors)},
Title = {Verifying Reliability (Dagstuhl Seminar 12341).},
Journal = {<em>Dagstuhl Reports</em>.},
Year = {(2012).},
Pages = {57-73},
Note = {gfey, CE},
Isbn = {http://dx.doi.org/10.4230/DagRep.2.8.57},
Howpublished = {12-999 FFM+:2012 {DAGSTUHL REPORTS}}
}

@article{FFM+:2012b,
Author = {Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (Organizers)},
Title = {Verifying Reliability (Dagstuhl Seminar 12341).},
Journal = {<em>Dagstuhl Reports</em>.},
Year = {(2012).},
Note = {gfey, CE},
Howpublished = {12-999 FFM+:2012b {DAGSTUHL REPORTS}}
}

@misc{Falk12,
Author = {Heiko Falk},
Title = {Reconciling Compilation and Timing Analysis.},
Year = {(2012).},
Month = {October},
Note = {hfalk, ESD, tacle, WCC},
Series = {20121009-emsoft-invited_talk-falk.pdf},
Address = {Tampere / Finland},
Howpublished = {12-15 Falk12 EMSOFT},
Type = {Invited Talk at the International Conference on Embedded Software (EMSOFT),}
}

@misc{FaKl12,
Author = {Heiko Falk and Jan C. Kleinsorge},
Title = {Reconciling Compilers and Timing Analysis for Safety-Critical Real-Time Systems - the WCET-aware C Compiler WCC.},
Year = {(2012).},
Month = {March},
Note = {hfalk, ESD, emp2, WCC},
Series = {20120331-cgo-tutorial.pdf},
Address = {San Jose / USA},
Howpublished = {12-75 FaKl12 CGO},
Type = {Tutorial at the International Symposium on Code Generation and Optimization (CGO),}
}

@article{FaMa12,
Author = {Heiko Falk and Peter Marwedel (Eds.)},
Title = {Introduction to the Special Section on SCOPES'09.},
Journal = {<em>ACM Transactions on Embedded Computing Systems (TECS)</em>.},
Year = {(2012).},
Volume = {<strong>11S</strong>.},
Number = {(1),},
Pages = {17:1-17:3},
Month = {June},
Note = {hfalk, ESD},
Publisher = {ACM:},
Series = {201206-tecs-falk.pdf},
Isbn = {10.1145/2180887.2180894},
Howpublished = {12-50 FaMa12 TECS}
}

@proceedings{FaYi12,
Author = {Heiko Falk and Wang Yi (Eds.)},
Title = {Proceedings of the 13th International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES).},
Year = {(2012).},
Month = {June},
Note = {hfalk, ESD},
Address = {Beijing / China},
Howpublished = {12-55 FaYi12 LCTES},
Url = {http://lctes12.cs.purdue.edu}
}

@inproceedings{FHL+12,
Author = {Heiko Falk, Kevin Hammond, Kim G. Larsen, Bj&ouml;rn Lisper and Stefan M. Petters},
Title = {Code-Level Timing Analysis of Embedded Software.},
Year = {(2012).},
Pages = {163-164},
Month = {October},
Note = {hfalk, ESD, tacle},
Series = {20121009-emsoft-falk.pdf},
Address = {Tampere / Finland},
Isbn = {10.1145/2380356.2380386},
Howpublished = {12-20 FHL+12 EMSOFT},
Booktitle = {<em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em>},
Abstract = {Embedded systems are often business- or safety-critical, with strict timing requirements that have to be met for the information-processing. Code-level timing analysis (used to analyse software running on some given hardware w. r. t. its timing properties) is an indispensable technique for ascertaining whether or not these requirements are met. However, recent developments in hardware, especially multi-core processors, and in software organisation render analysis increasingly more difficult, thus challenging the evolution of timing analysis techniques. This special session aims to give an overview over the current state of the art and the future challenges w. r. t. code-level timing analysis and introduces TACLe, a recently started EU-funded networking activity targeting these challenges.}
}

@inbook{FML12,
Author = {Heiko Falk, Peter Marwedel and Paul Lokuciejewski},
Title = {Reconciling Compilation and Timing Analysis.},
Year = {(2012).},
Pages = {145-170},
Month = {March},
Note = {hfalk, ESD, emp2, WCC},
Editor = {In S. Chakraborty and J. Ebersp&auml;cher (Eds.)},
Publisher = {Springer:},
Isbn = {10.1007/978-3-642-24349-3_7},
Howpublished = {12-80 FML12 Springer},
Booktitle = {<em>Advances in Real-Time Systems</em>},
chapter = {7},
Abstract = {Timing constraints must be respected for embedded real-time applications. Traditionally, compilers are unable to use precise estimates of execution times for optimization, and timing properties of code are derived after compilation. A number of design iterations are required if timing constraints are not met. We propose to reconcile compilers and timing analysis and to create a worst-case execution time (WCET) aware compiler in this way. Such WCET-aware compilers can exploit precise WCET information during compilation. This way, they are able to improve the code quality. Also, we may be able to avoid some of the design iterations.<br /> In this chapter, we describe the integration of a compiler and a WCET analyzer, yielding our WCET-aware compiler WCC. We are then reconsidering standard compiler optimizations for their potential to reduce the WCET, assuming that the WCET is now used as the cost function. Considered optimizations include function inlining, loop unrolling, loop unswitching, register allocation, scratchpad memory allocation, and cache partitioning. For a set of benchmarks, average WCET reductions of up to 40% were observed. The results indicate that this new area of research has the potential of achieving worthwhile execution time reductions for real-time code.}
}

@inproceedings{RF:2012,
Author = {Heinz Riener and Goerschwin Fey},
Title = {Model-Based Diagnosis versus Error Explanation.},
Year = {(2012).},
Pages = {43-52},
Note = {gfey, CE},
Howpublished = {12-999 RF:2012 MEMOCODE},
Booktitle = {<em>ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE)</em>}
}

@inproceedings{RF:2012c,
Author = {Heinz Riener and Goerschwin Fey},
Title = {Model-Based Diagnosis versus Error Explanation.},
Year = {(2012).},
Note = {gfey, CE},
Howpublished = {12-999 RF:2012c SLDAES},
Booktitle = {<em>International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES)</em>}
}

@inproceedings{RF:2012b,
Author = {Heinz Riener and Goerschwin Fey},
Title = {FAUST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.},
Year = {(2012).},
Pages = {234-240},
Note = {gfey, CE},
Howpublished = {12-999 RF:2012b SPIN},
Booktitle = {<em>International SPIN Workshop on Model Checking of Software (SPIN)</em>}
}

@unpublished{Rai:2012,
Author = {Jaan Raik (Organizer)},
Title = {Panel: Can RTL test techniques be applied to software?.},
Year = {(2012).},
Note = {gfey, CE},
Howpublished = {12-999 Rai:2012}
}

@inproceedings{MFF:2012,
Author = {Jan Malburg and Alexander Finder and Goerschwin Fey},
Title = {Automated Feature Localization for Hardware Designs using Coverage Metrics.},
Year = {(2012).},
Pages = {941-946},
Note = {gfey, CE},
Howpublished = {12-999 MFF:2012 DAC},
Booktitle = {<em>Design Automation Conference (DAC)</em>}
}

@inproceedings{MFF:2012b,
Author = {Jan Malburg and Alexander Finder and Goerschwin Fey},
Title = {Automated Feature Localization for Hardware Designs using Coverage Metrics.},
Year = {(2012).},
Note = {gfey, CE},
Howpublished = {12-999 MFF:2012b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@book{Zimm12,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2012).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20120711-computability-theory-zimmermann.pdf},
Edition = {2.},
Isbn = {10.15480/882.1064},
Howpublished = {12-40 Zimm12 TUBdok},
Abstract = {This book is a development of class notes for a two-hour lecture including a one-hour lab held for second-year Bachelor students of Computer Science at the Hamburg University of Technology during the last four years. The course aims to present the basic results of computability theory, including mathematical models of computability, primitive recursive and partial recursive functions, Ackermann's function, G&ouml;del numbering, universal functions, smn theorem, Kleene's normal form, undecidable sets, theorems of Rice, and word problems. The manuscript has partly grown out of notes taken by the author during his studies at the University of Erlangen-Nuremberg. The second edition contains minor changes. In particular, the section on G&ouml;del numbering has been rewritten and a glossary of terms has been added.}
}

@inproceedings{SRW+:2012,
Author = {Mathias Soeken and Heinz Riener and Robert Wille and Goerschwin Fey and Rolf Drechsler},
Title = {Verification of Embedded Systems Using Modeling and Implementation Languages.},
Year = {(2012).},
Pages = {67-72},
Note = {gfey, CE},
Howpublished = {12-999 SRW+:2012 MECOES},
Booktitle = {<em>International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs)</em>}
}

@inproceedings{DF:2012d,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Automated Debugging from Pre-Silicon to Post-Silicon.},
Year = {(2012).},
Note = {gfey, CE},
Howpublished = {12-999 DF:2012d TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{DF:2012b,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Automated Post-Silicon Debugging of Failing Speedpaths.},
Year = {(2012).},
Pages = {13-18},
Note = {gfey, CE},
Howpublished = {12-999 DF:2012b ATS},
Booktitle = {<em>Asian Test Symposium (ATS)</em>}
}

@inproceedings{DF:2012c,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Application of Timing Variation Modeling to Speedpath Diagnosis.},
Year = {(2012).},
Pages = {34-37},
Note = {gfey, CE},
Howpublished = {12-999 DF:2012c S4D},
Booktitle = {<em>System, Software, SoC and Silcon Debug Conference (S4D)</em>}
}

@inproceedings{DF:2012,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Automated Debugging from Pre-Silicon to Post-Silicon.},
Year = {(2012).},
Pages = {324-329},
Note = {gfey, CE},
Howpublished = {12-999 DF:2012 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{DFRR:2012c,
Author = {Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan},
Title = {On Modeling and Evaluation of Logic Circuits Under Timing Variations.},
Year = {(2012).},
Pages = {431-436},
Note = {gfey, CE},
Howpublished = {12-999 DFRR:2012c DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{DFRR:2012b,
Author = {Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan},
Title = {Functional Analysis of Circuits Under Timing Variations.},
Year = {(2012).},
Pages = {45-50},
Note = {gfey, CE},
Howpublished = {12-999 DFRR:2012b EDAWS},
Booktitle = {<em>edaWorkshop</em>}
}

@inproceedings{DFRR:2012,
Author = {Mehdi Dehbashi and Goerschwin Fey and Kaushik Roy and Anand Raghunathan},
Title = {Functional Analysis of Circuits Under Timing Variations.},
Year = {(2012).},
Pages = {177},
Note = {gfey, CE},
Howpublished = {12-999 DFRR:2012 ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@phdthesis{Saleemi12,
Author = {Mehwish Saleemi},
Title = {Coding Theory via Groebner Bases.},
Year = {(2012).},
Month = {October},
Note = {AEG},
Series = {20121029-phdthesis-saleemi.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.1081},
Howpublished = {12-05 Saleemi12 PhD},
Type = {Ph.D. Thesis.},
School = {Hamburg University of Technology},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {Coding theory plays an important role in efficient transmission of data over noisy channels. In this thesis efficient encoding procedure for linear codes is developed using an algebraic approach. Description of linear codes as ideals in a residue class ring are given in terms of Groebner basis. While investigating primitive Reed Muller codes, a special family of linear codes with designed Hamming distance is obtained. A result proves their superiority over existing primitive Reed Muller codes. Furthermore, codes associated to a particular binomial ideal, defined as a sum of toric ideal and a prime ideal, are explored through minimal generators and Groebner basis. For these non-toric binomial ideals universal Groebner bases, Graver bases and circuits are also found. It is shown that each such binomial ideal has a natural reduced Groebner basis which provides a very compact encoding procedure. Finally, the binomial ideal of a linear code is presented in terms of its syzygy modules and the corresponding finite free resolution is also given.}
}

@article{HaZi12,
Author = {Muhammad Kashif Hanif and Karl-Heinz Zimmermann},
Title = {Graphics card processing: accelerating profile-profile alignment.},
Journal = {<em>Central European Journal of Computer Science (CEJCS)</em>.},
Year = {(2012).},
Volume = {<strong>2</strong>.},
Number = {(4),},
Pages = {367-388},
Month = {December},
Note = {khzimmermann, AEG},
Publisher = {De Gruyter Open:},
Isbn = {10.2478/s13537-012-0033-5},
Howpublished = {12-03 HaZi12 CEJCS},
Abstract = {Alignment is the fundamental operation in molecular biology for comparing biomolecular sequences. The most widely used method for aligning groups of alignments is based on the alignment of the profiles corresponding to the groups. We show that profile-profile alignment can be significantly speeded up by general purpose computing on a modern commodity graphics card. Wavefront and matrix-matrix product approaches for implementing profile-profile alignment onto graphics processor are analyzed. The average speed-up obtained is one order of magnitude even when overheads are considered. Thus the computational power of graphics cards can be exploited to develop improved solutions for multiple sequence alignment.}
}

@article{DuZi12b,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {A variant of the Gr&ouml;bner basis algorithm for computing Hilbert bases.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2012).},
Volume = {<strong>81</strong>.},
Number = {(1),},
Pages = {145-155},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20121116-dueck-ijpam.pdf},
Howpublished = {12-04 DuZi12b IJPAM},
Abstract = {Gr&ouml;bner bases can be used for computing the Hilbert basis of a numerical submonoid. By using these techniques, we provide an algorithm that calculates a basis of a subspace of a finite-dimensional vector space over a finite prime field given as a matrix kernel.}
}

@article{DuZi12a,
Author = {Natalia D&uuml;ck and Karl-Heinz Zimmermann},
Title = {Standard bases for linear codes.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2012).},
Volume = {<strong>80</strong>.},
Number = {(3),},
Pages = {315-329},
Month = {October},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20121026-dueck-ijpam.pdf},
Howpublished = {12-10 DuZi12a IJPAM},
Abstract = {Each linear code can be described by a binomial ideal given as the sum of a toric ideal and a non-prime ideal. For binary linear codes, we provide standard bases for the localizations of the code ideals.}
}

@phdthesis{Reyes12,
Author = {Oscar Mauricio Reyes Torres},
Title = {Neural Synchronization and Light-weight Cryptography in Embedded Systems.},
Year = {(2012).},
Month = {August},
Note = {AEG},
Publisher = {Shaker:},
Address = {Hamburg / Germany},
Isbn = {10.2370/9783844012330},
Howpublished = {12-35 Reyes12 PhD},
Type = {Ph.D. Thesis.},
School = {Hamburg University of Technology},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {Synchronization is a phenomenon that is widely studied in different fields. In the case of artificial neural networks, two feed-forward networks can eventually synchronize by exchanging their outputs and applying a suitable learning rule. The dynamics of this process has been studied for the so-called permutation parity machine. This is a binary variant of the well-known tree parity machine in which the weights are small integers that are not adjusted, but completely replaced during each learning step. In the permutation parity machine, a new set of weights is pseudo-randomly drawn from a pool of binary data after the outputs have been exchanged. Synchronization is a result of competing stochastic forces given by a sequence of increasing and decreasing overlaps. This sequence constitutes a random process endowed with the Markov property. More concretely, the mutual learning process can be described by a first-order Markov chain where synchronization amounts to the stationarity of the chain.<br /> Nowadays, cryptography plays an ever more important role in information security given the countless scenarios in which information exchange requires different levels of privacy, secrecy or reliability. To this end, cryptographic algorithms based on neural synchronization can be used, since mutual learning leads to synchronization much faster than learning by examples.<br /> In this work, a key exchange protocol based on permutation parity machines has been studied. It has been proved that even though the weights used during each learning step are not strongly correlated, synchronization still occurs. Moreover, the lack of correlation among the weights during the synchronization process makes the key exchange protocol robust not only against common attacks, e.g. simple or geometric attacks, but also against attacks based on non-standard schemes, such as majority, genetic or probabilistic attacks.<br /> Permutation parity machines make use of a more complex learning rule than the tree parity machines, especially due to the process of weight assignment. Nevertheless, the simplicity of the network compensates for the complexity of the learning rule in terms of hardware implementation. Additionally, the use of a permutation network based on a linear feedback shift register helps to reduce considerably the complexity in the assignment of the weights during the learning step.<br /> The key exchange protocol based on permutation parity machines does not require lengthy mathematical calculations and so is suitable for implementation by embedded systems where hardware constraints are decisive. Various alternatives of hardware implementations have been considered, including FPGA, RISC MCU, RFID tags and NFC devices.}
}

@techreport{AEF+12,
Author = {Philip Axer, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan, Bengt Jonsson, Peter Marwedel, Jan Reineke, Christine Rochange, Maurice Sebastian, Reinhard von Hanxleden, Reinhard Wilhelm and Wang Yi},
Title = {Building Timing Predictable Embedded Systems.},
Year = {(2012).},
Number = {(#2012-013),},
Month = {July},
Note = {hfalk, ESD, tacle, WCC},
Series = {20120703-report-2012-013-axer.pdf},
Address = {Uppsala / Sweden},
Howpublished = {12-45 AEF+12 Uppsala},
Type = {Technical Report},
School = {Uppsala University},
Institution = {Department of Information Technology},
Abstract = {A large class of embedded systems is distinguished from general purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of nondeterminism and make guarantees harder to provide. The intention of this paper is to summarize current state-of-the-art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstractions levels in embedded software design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach based on the synchronous paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally we discuss how to handle predictability at the level of networked embedded systems, where randomly occurring errors must be considered.}
}

@inproceedings{BDF+:2012,
Author = {Roderick Bloem and Rolf Drechsler and Goerschwin Fey and Alexander Finder and Georg Hofferek and Robert Könighofer and Jaan Raik and Urmas Repinski and André Sülflow},
Title = {FoREnSiC - An Automatic Debugging Environment for C Programs.},
Year = {(2012).},
Pages = {260-265},
Note = {gfey, CE},
Howpublished = {12-999 BDF+:2012 HVC},
Booktitle = {<em>IBM Haifa Verification Conference (HVC)</em>}
}

@inproceedings{PFKM12,
Author = {Sascha Plazar, Heiko Falk, Jan C. Kleinsorge and Peter Marwedel},
Title = {WCET-aware Static Locking of Instruction Caches.},
Year = {(2012).},
Pages = {44-52},
Month = {April},
Note = {hfalk, ESD, emp2, WCC},
Series = {20120402-cgo-plazar.pdf},
Address = {San Jose / USA},
Isbn = {10.1145/2259016.2259023},
Howpublished = {12-70 PKFM12 CGO},
Booktitle = {<em>In Proceedings of the International Symposium on Code Generation and Optimization (CGO)</em>},
Abstract = {In the past decades, embedded system designers moved from simple, predictable system designs towards complex systems equipped with caches. This step was necessary in order to bridge the increasingly growing gap between processor and memory system performance. Static analysis techniques had to be developed to allow the estimation of the cache behavior and an upper bound of the execution time of a program. This bound is called worst-case execution time (WCET). Its knowledge is crucial to verify whether hard real-time systems satisfy their timing constraints, and the WCET is a key parameter for the design of embedded systems.<br /> In this paper, we propose a WCET-aware optimization technique for static I-cache locking which improves a program's performance and predictability. To select the memory blocks to lock into the cache and avoid time consuming repetitive WCET analyses, we developed a new algorithm employing integer-linear programming (ILP). The ILP models the worst-case execution path (WCEP) of a program and takes the influence of locked cache contents into account. By modeling the effect of locked memory blocks on the runtime of basic blocks, the overall WCET of a program can be minimized. We show that our optimization is able to reduce the estimated WCET (abbr. WCETest) of real-life benchmarks by up to 40.8%. At the same time, our proposed approach is able to outperform a regular cache by up to 23.8% in terms of WCETest.}
}

@inproceedings{FFA+:2012,
Author = {Stefan Frehse and Goerschwin Fey and Eli Arbel and Karen Yorav and Rolf Drechsler},
Title = {Complete and Effective Robustness Checking by Means of Interpolation.},
Year = {(2012).},
Pages = {82-90},
Note = {gfey, CE},
Howpublished = {12-999 FFA+:2012 FMCAD},
Booktitle = {<em>Formal Methods in Computer-Aided Design (FMCAD)</em>}
}

@inproceedings{FRF:2012,
Author = {Stefan Frehse and Heinz Riener and Goerschwin Fey},
Title = {Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz.},
Year = {(2012).},
Pages = {90-96},
Note = {gfey, CE},
Howpublished = {12-999 FRF:2012 ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@inproceedings{CCR+12,
Author = {Sudipta Chattopadhyay, Lee Kee Chong, Abhik Roychoudhury, Timon Kelter, Heiko Falk and Peter Marwedel},
Title = {A Unified WCET Analysis Framework for Multi-core Platforms.},
Year = {(2012).},
Pages = {99-108},
Month = {April},
Note = {hfalk, ESD, emp2, WCC},
Series = {20120418-rtas-chattopadhyay.pdf},
Address = {Beijing / China},
Isbn = {10.1109/RTAS.2012.26},
Howpublished = {12-65 CCR+12 RTAS},
Booktitle = {<em>In Proceedings of the 18th Real-Time and Embedded Technology and Applications Symposium (RTAS)</em>},
Abstract = {With the advent of multi-core architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this paper, we propose a unified WCET analysis framework for multi-core processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multi-core architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.}
}

@phdthesis{Torgasin12,
Author = {Svetlana Torgasin},
Title = {Graph-based Methods for the Design of DNA Computations.},
Year = {(2012).},
Month = {January},
Note = {AEG},
Series = {20120115-phdthesis-torgasin.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.1049},
Howpublished = {12-95 Torgasin12 PhD},
Type = {Ph.D. Thesis.},
School = {Hamburg University of Technology},
Institution = {School of Electrical Engineering, Computer Science and Mathematics},
Abstract = {The reliability of results in DNA based computations strongly depends on the DNA sequences representing the units of information. The task of finding appropriate sequences is currently handled by means of conventional computing. The most accurate criterium for this purpose is the free energy of hybridization complexes built by two DNA single strands. This thesis addresses two issues in this area. First, finding of a secondary structure of DNA/DNA complexes having minimal free energy. For this, a novel graph-based representation of DNA/DNA complexes is introduced and two advanced methods calculating the free energy based on dynamic programming are proposed. Second, the validation of a given set of DNA words to encode a particular assignment of a mathematical problem. For this, a method is developed based on free energy assessment. It is suitable for DNA computing models that are based on an interdependent encoding of DNA words, which represent two different types of entities in the mathematical problem. Another accomplishment of the thesis is an optimization of the Floyd-Warshall algorithm for finding shortest paths in a weighted graph. A memory reduction method for the particular case of bipartite graphs is established.}
}

@article{KWZ12,
Author = {Wolfgang Kramper, Ralf Wanker and Karl-Heinz Zimmermann},
Title = {Analysis of swarm behavior using compound eye and neural network control.},
Journal = {<em>Central European Journal of Computer Science (CEJCS)</em>.},
Year = {(2012).},
Volume = {<strong>2</strong>.},
Number = {(1),},
Pages = {16-32},
Month = {March},
Note = {khzimmermann, AEG},
Publisher = {De Gruyter Open:},
Isbn = {10.2478/s13537-012-0004-x},
Howpublished = {12-85 KWZ12 CEJCS},
Abstract = {The emergent collective intelligence of groups of simple agents known as swarm intelligence is a new exiting way of achieving a form of artificial intelligence. This paper studies a formal model for swarm intelligence inspired by biological swarms found in nature. Software agents are used to model the individuals of a swarm. Each agent is controlled by a neural network that processes position data from the others in its visible zone given by a compound eye and in this way navigates in 3D space. An additional input parameter is used to represent the agent's motivation to form a swarm. Simulations with different motivation parameters exhibit remarkable agent formations that can be considered as biologically plausable. Several ways to improve the model are discussed.}
}

@inproceedings{FSF:2011b,
Author = {Alexander Finder and André Sülflow and Goerschwin Fey},
Title = {Latency Analysis for Sequential Circuits.},
Year = {(2011).},
Pages = {119-124},
Note = {gfey, CE},
Howpublished = {11-999 FSF:2011b TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{FSF:2011,
Author = {Alexander Finder and André Sülflow and Goerschwin Fey},
Title = {Latency Analysis for Sequential Circuits.},
Year = {(2011).},
Pages = {129-134},
Note = {gfey, CE},
Isbn = {10.1109/ETS.2011.34},
Howpublished = {11-999 FSF:2011 ETS},
Booktitle = {<em>IEEE European Test Symposium (ETS)</em>}
}

@incollection{GFD:2011,
Author = {Daniel Große and Goerschwin Fey and Rolf Drechsler},
Title = {Enhanced Formal Verification Flow for Circuits Integrating Debugging.},
Year = {(2011).},
Pages = {119-129},
Note = {gfey, CE},
Howpublished = {11-999 GFD:2011 {DESIGN AND TEST TECHNOLOGY FOR DEPENDABLE SYSTEMS-ON-CHIP}},
Booktitle = {<em>Design and Test Technology for Dependable Systems-on-Chip</em>}
}

@inproceedings{HFF+:2011,
Author = {Finn Haedicke and Stefan Frehse and Goerschwin Fey and Daniel Große and Rolf Drechsler},
Title = {metaSMT: Focus on Your Application not on Solver Integration.},
Year = {(2011).},
Pages = {22-29},
Note = {gfey, CE},
Howpublished = {11-999 HFF+:2011 DIFTS},
Booktitle = {<em>Int'l Workshop on Design and Implementation of Formal Tools and Systems (DIFTS)</em>}
}

@inproceedings{Fey:2011c,
Author = {Goerschwin Fey},
Title = {Assessing System Vulnerability using Formal Verification Techniques.},
Year = {(2011).},
Note = {gfey, CE},
Howpublished = {11-999 Fey:2011c MEMICS},
Booktitle = {<em>Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS)</em>}
}

@inproceedings{Fey:2011,
Author = {Goerschwin Fey},
Title = {Orchestrated Multi-Level Information Flow Analysis to Understand SoCs.},
Year = {(2011).},
Pages = {284-285},
Note = {gfey, CE},
Howpublished = {11-999 Fey:2011 DAC},
Booktitle = {<em>Design Automation Conference (DAC)</em>}
}

@article{FSFD:2011,
Author = {Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler},
Title = {Effective Robustness Analysis using Bounded Model Checking Techniques.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2011).},
Pages = {1239-1252},
Note = {gfey, CE},
Isbn = {10.1109/TCAD.2011.2120950},
Howpublished = {11-999 FSFD:2011 TCAD}
}

@inproceedings{FaKo11,
Author = {Heiko Falk and Helena Kotthaus},
Title = {WCET-driven Cache-aware Code Positioning.},
Year = {(2011).},
Pages = {145-154},
Month = {October},
Note = {hfalk, ESD, WCC},
Series = {20111011-cases-falk.pdf},
Address = {Taipei / Taiwan},
Isbn = {10.1145/2038698.2038722},
Howpublished = {11-40 FaKo11 CASES},
Booktitle = {<em>In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)</em>},
Type = {<strong>Best Paper Candidate</strong>.},
Abstract = {Code positioning is a well-known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of code fragments in memory avoids overlapping of cache sets and thus decreases the number of cache conflict misses.<br /> We present a novel cache-aware code positioning optimization driven by worst-case execution time (WCET) information. For this purpose, we introduce a formal cache model based on a conflict graph which is able to capture a broad class of cache architectures. This cache model is combined with a formal WCET timing model, resulting in a cache conflict graph weighted with WCET data. This conflict graph is then exploited by heuristics for code positioning of both basic blocks and entire functions.<br /> Code positioning is able to decrease the accumulated cache misses for a total of 18 real-life benchmarks by 15.5% on average for an automotive processor featuring a 2-way set-associative cache. These cache miss reductions translate to average WCET reductions by 6.1%. For direct-mapped caches, even larger savings of 18.8% (cache misses) and 9.0% (WCET) were achieved.}
}

@inproceedings{FSS11,
Author = {Heiko Falk, Norman Schmitz and Florian Schmoll},
Title = {WCET-aware Register Allocation based on Integer-Linear Programming.},
Year = {(2011).},
Pages = {13-22},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20110706-ecrts-falk.pdf},
Address = {Porto / Portugal},
Isbn = {10.1109/ECRTS.2011.10},
Howpublished = {11-85 FSS11 ECRTS},
Booktitle = {<em>In Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS)</em>},
Abstract = {Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is register allocation. Many compilers heuristically decide when and where to spill a register to memory, without having a clear understanding of the impact of such spill code on a program's runtime.<br /> This paper presents an integer-linear programming (ILP) based register allocator that uses precise worst-case execution time (WCET) models. Using this WCET timing data, the compiler avoids spill code generation along the critical path defining a program's WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware ILP-based register allocator. Our results underline the effectiveness of the proposed techniques. For a total of 55 realistic benchmarks, we reduced WCETs by 20.2% on average and ACETs by 14%, compared to a standard graph coloring allocator. Furthermore, our ILP-based register allocator outperforms a WCET-aware graph coloring allocator by more than a factor of two for the considered benchmarks, while requiring less runtime.}
}

@inproceedings{RBF:2011,
Author = {Heinz Riener and Roderick Bloem and Goerschwin Fey},
Title = {Test Case Generation from Mutants using Model Checking Techniques.},
Year = {(2011).},
Pages = {388-397},
Note = {gfey, CE},
Howpublished = {11-999 RBF:2011 MUTATION},
Booktitle = {<em>Mutation</em>}
}

@inproceedings{KFM11,
Author = {Jan C. Kleinsorge, Heiko Falk and Peter Marwedel},
Title = {A Synergetic Approach to Accurate Analysis of Cache-Related Preemption Delay.},
Year = {(2011).},
Pages = {329-338},
Month = {October},
Note = {hfalk, ESD, WCC},
Series = {20111012-emsoft-kleinsorge.pdf},
Address = {Taipei / Taiwan},
Isbn = {10.1145/2038642.2038693},
Howpublished = {11-30 KFM11 EMSOFT},
Booktitle = {<em>In Proceedings of the International Conference on Embedded Software (EMSOFT)</em>},
Abstract = {The worst-case execution time (WCET) of a task denotes the largest possible execution time for all possible inputs and thus, hardware states. For non-preemptive multitask scheduling, techniques for the static estimation of safe upper bounds have been subject to industrial practice for years. For preemptive scheduling however, the isolated analysis of tasks becomes imprecise as interferences among tasks cannot be considered with sufficient precision. For such scenarios, the cache-related preemption delay (CRPD) denotes a key metric as it reflects the effects of preemptions on the execution behavior of a single task. Until recently, proposals for CRPD analyses were often limited to direct mapped caches or comparably imprecise for k-way set-associative caches.<br /> In this paper, we propose how the current best techniques for CRPD analysis, which have only been proposed separately and for different aspects of the analysis can be brought together to construct an efficient CRPD analysis with unique properties. Moreover, along the construction, we propose several different enhancements to the methods employed. We also exploit that in a complete approach, analysis steps are synergetic and can be combined into a single analysis pass solving all formerly separate steps at once. In addition, we argue that it is often sufficient to carry out the combined analysis on basic block bounds, which further lowers the overall complexity. The result is a proposal for a fast CRPD analysis of very high accuracy.}
}

@book{Zimm11,
Author = {Karl-Heinz Zimmermann},
Title = {Computability Theory.},
Year = {(2011).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Hamburg University of Technology:},
Series = {20110729-computability-theory-zimmermann.pdf},
Edition = {1.},
Isbn = {10.15480/882.1012},
Howpublished = {11-75 Zimm11 TUBdok},
Abstract = {Why do we need a formalization of the notion of algorithm or effective computation? In order to show that a specific problem is algorithmically solvable, it is sufficient to provide an algorithm that solves it in a sufficiently precise manner. However, in order to prove that a problem is in principle not solvable by an algorithm, a rigorous formalism is necessary that allows mathematical proofs. The need for such a formalism became apparent in the works of David Hilbert (1900) on the foundations of mathematics and Kurt G&ouml;del (1931) on the incompleteness of elementary arithmetic. The first investigations in the field were conducted by the logicians Alonzo Church, Stephen Kleene, Emil Post, and Alan Turing in the early 1930s. They provided the foundation of computability theory as a branch of theoretical computer science. The fundamental results established Turing computability as the correct formalization of the informal idea of effective calculation. The results led to Church's thesis stating that "everything computable is computable by a Turing machine". The theory of computability has grown rapidly from its beginning. Its questions and methods are penetrating many other mathematical disciplines. Today, computability theory provides an important theoretical background for logicians and computer scientists. Many mathematical problems are known to be undecidable such as the word problem for groups and semigroups, the halting problem, and Hilbert's tenth problem.}
}

@inproceedings{SKF+:2011,
Author = {Mathias Soeken and Ulrich Kühne and Martin Freibothe and Goerschwin Fey and Rolf Drechsler},
Title = {Towards Automatic Property Generation for the Formal Verification of Bus Bridges.},
Year = {(2011).},
Pages = {417-422},
Note = {gfey, CE},
Howpublished = {11-999 SKF+:2011 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{SKF+:2011b,
Author = {Mathias Soeken and Ulrich Kühne and Martin Freibothe and Goerschwin Fey and Rolf Drechsler},
Title = {Towards Automatic Property Generation for the Formal Verification of Bus Bridges.},
Year = {(2011).},
Note = {gfey, CE},
Howpublished = {11-999 SKF+:2011b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{DSF:2011,
Author = {Mehdi Dehbashi and André Sülflow and Goerschwin Fey},
Title = {Automated Design Debugging in a Testbench-Based Verification Environment.},
Year = {(2011).},
Pages = {479-486},
Note = {gfey, CE},
Howpublished = {11-999 DSF:2011 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{DF:2011,
Author = {Mehdi Dehbashi and Goerschwin Fey},
Title = {Automated Post-Silicon Debugging of Design Bugs.},
Year = {(2011).},
Pages = {67-71},
Note = {gfey, CE},
Howpublished = {11-999 DF:2011 S4D},
Booktitle = {<em>System, Software, SoC and Silcon Debug Conference (S4D)</em>}
}

@article{SaZi11,
Author = {Mehwish Saleemi and Karl-Heinz Zimmermann},
Title = {Groebner bases for linear codes over GF(4).},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2011).},
Volume = {<strong>73</strong>.},
Number = {(4),},
Pages = {435-442},
Month = {December},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20111201-saleemi-ijpam.pdf},
Howpublished = {11-20 SaZi11 IJPAM},
Abstract = {A linear code over a prime field can be described by a binomial ideal in a polynomial ring given as the sum of a toric ideal and a nonprime ideal. A Groebner basis for such an ideal can be read off from a systematic generator matrix of the corresponding code. In this paper, a similar result will be presented for linear codes over GF(4). To this end, the extented alphabet GF(4) is dealt with by enlarging the polynomial ring.}
}

@article{LPF+11,
Author = {Paul Lokuciejewski, Sascha Plazar, Heiko Falk, Peter Marwedel and Lothar Thiele},
Title = {Approximating Pareto optimal compiler optimization sequences-a trade-off between WCET, ACET and code size.},
Journal = {<em>Software: Practice and Experience</em>.},
Year = {(2011).},
Volume = {<strong>41</strong>.},
Number = {(12),},
Pages = {1437-1458},
Month = {November/December},
Note = {hfalk, ESD, WCC},
Publisher = {John Wiley & Sons:},
Series = {20111112-spe-lokuciejewski.pdf},
Isbn = {10.1002/spe.1079},
Howpublished = {11-25 LPF+11 SPE},
Abstract = {With the growing complexity of embedded systems software, high code quality can only be achieved using a compiler. Sophisticated compilers provide a vast spectrum of various optimizations to improve code aggressively w.r.t. different objective functions, e.g. average-case execution time (ACET) or code size. Owing to the complex interactions between the optimizations, the choice for a promising sequence of code transformations is not trivial. Compiler developers address this problem by proposing standard optimization levels, e.g. O3 or Os. However, previous studies have shown that these standard levels often miss optimization potential or might even result in performance degradation. In this paper, we propose the first adaptive worst-case execution time (WCET)-aware compiler framework for an automatic search of compiler optimization sequences that yield highly optimized code. Besides the objective functions ACET and code size, we consider the WCET which is a crucial parameter for real-time systems. To find suitable trade-offs between these objectives, stochastic evolutionary multi-objective algorithms identifying Pareto optimal solutions for the objectives WCET/ACET and WCET/code size are exploited. A comparison based on statistical performance assessments is performed that helps to determine the most suitable multi-objective optimizer. The effectiveness of our approach is demonstrated on real-life benchmarks showing that standard optimization levels can be significantly outperformed.}
}

@article{LSZ11,
Author = {Robert Leppert, Mehwish Saleemi and Karl-Heinz Zimmermann},
Title = {Groebner bases for quaternary codes.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2011).},
Volume = {<strong>71</strong>.},
Number = {(4),},
Pages = {595-608},
Month = {October},
Note = {rleppert, khzimmermann, AEG},
Publisher = {AP:},
Series = {20111005-leppert-ijpam.pdf},
Howpublished = {11-55 LSZ11 IJPAM},
Abstract = {A linear code can be described by a binomial ideal in a polynomial ring, given as the sum of a toric ideal and a nonprime ideal. A Groebner basis for such an ideal can be read off from a systematic generator matrix for the corresponding code. In this paper, an analogue result will be presented for quaternary codes.}
}

@misc{CNF+11,
Author = {Samarjit Chakraborty, Marco Di Natale, Heiko Falk, Martin Lukasiewyzc and Frank Slomka},
Title = {Timing and Schedulability Analysis for Distributed Automotive Control Applications.},
Year = {(2011).},
Pages = {349-350},
Month = {October},
Note = {hfalk, ESD, WCC},
Series = {20111009-emsoft-tutorial.pdf},
Address = {Taipei / Taiwan},
Isbn = {10.1145/2038642.2038696},
Howpublished = {11-45 CNF+11 EMSOFT},
Type = {Tutorial at the International Conference on Embedded Software (EMSOFT),},
Abstract = {High-end cars today consist of more than 100 electronic control units (ECUs) that are connected to a set of sensors and actuators and run multiple distributed control applications. The design flow of such architectures consists of specifying control applications as Simulink/Stateflow models, followed by generating code from them and finally mapping such code onto multiple ECUs. In addition, the scheduling policies and parameters on both the ECUs and the communication buses over which they communicate also need to be specified. These policies and parameters are computed from high-level timing and control performance constraints. The proposed tutorial will cover different aspects of this design flow, with a focus on timing and schedulability problems. After reviewing the basic concepts of worst-case execution time analysis and schedulability analysis, we will discuss the differences between meeting timing constraints (as in classical real-time systems) and meeting control performance constraints (e.g., stability, steady and transient state performance). We will then describe various control performance related schedulability analysis techniques and how they may be tied to model-based software development. Finally, we will discuss various schedule synthesis techniques, both for ECUs as well as for communication protocols like FlexRay, so that control performance constraints specified at the model-level may be satisfied. Throughout the tutorial different commercial as well as academic tools will be discussed and demonstrated.}
}

@inproceedings{PKFM11,
Author = {Sascha Plazar, Jan C. Kleinsorge, Heiko Falk and Peter Marwedel},
Title = {WCET-driven Branch Prediction aware Code Positioning.},
Year = {(2011).},
Pages = {165-174},
Month = {October},
Note = {hfalk, ESD, WCC},
Series = {20111011-cases-plazar.pdf},
Address = {Taipei / Taiwan},
Isbn = {10.1145/2038698.2038724},
Howpublished = {11-35 PKFM11 CASES},
Booktitle = {<em>In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)</em>},
Abstract = {In the past decades, embedded system designers moved from simple, predictable system designs towards complex systems equipped with caches, branch prediction units and speculative execution. This step was necessary in order to fulfill increasing requirements on computational power. Static analysis techniques considering such speculative units had to be developed to allow the estimation of an upper bound of the execution time of a program. This bound is called worst-case execution time (WCET). Its knowledge is crucial to verify whether hard real-time systems satisfy their timing constraints, and the WCET is a key parameter for the design of embedded systems.<br /> In this paper, we propose a WCET-driven branch prediction aware optimization which reorders basic blocks of a function in order to reduce the amount of jump instructions and mispredicted branches. We employed a genetic algorithm which rearranges basic blocks in order to decrease the WCET of a program. This enables a first estimation of the possible optimization potential at the cost of high optimization runtimes. To avoid time consuming repetitive WCET analyses, we developed a new algorithm employing integer-linear programming (ILP). The ILP models the worst-case execution path (WCEP) of a program and takes branch prediction effects into account. This algorithm enables short optimization runtimes at slightly decreased optimization results. In a case study, the genetic algorithm is able to reduce the benchmarks' WCET by up to 24.7% whereas our ILP-based approach is able to decrease the WCET by up to 20.0%.}
}

@inproceedings{FHD+:2011,
Author = {Stefan Frehse and Finn Haedicke and Melanie Diepenbeck and Goerschwin Fey and Rolf Drechsler},
Title = {Hochoptimierter Ablauf zur Robustheitsprüfung.},
Year = {(2011).},
Pages = {35-42},
Note = {gfey, CE},
Howpublished = {11-999 FHD+:2011 ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@inproceedings{KFM+11b,
Author = {Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury},
Title = {Bus-Aware Multicore WCET Analysis through TDMA Offset&nbsp;Bounds.},
Year = {(2011).},
Pages = {3-12},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20110706-ecrts-kelter.pdf},
Address = {Porto / Portugal},
Isbn = {10.1109/ECRTS.2011.9},
Howpublished = {11-90 KFM+11b ECRTS},
Booktitle = {<em>In Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS)</em>},
Abstract = {In the domain of real-time systems, the analysis of the timing behavior of programs is crucial for guaranteeing the schedulability and thus the safeness of a system. Static analyses of the WCET (Worst-Case Execution Time) have proven to be a key element for timing analysis, as they provide safe upper bounds on a program's execution time. For single-core systems, industrial-strength WCET analyzers are already available, but up to now, only first proposals have been made to analyze the WCET in multicore systems, where the different cores may interfere during the access to shared resources. An important example for this are shared buses which connect the cores to a shared main memory. The time to gain access to the shared bus may vary significantly, depending on the used bus arbitration protocol and the access timings. In this paper, we propose a new technique for analyzing the duration of accesses to shared buses. We implemented a prototype tool which uses the new analysis and tested it on a set of realworld benchmarks. Results demonstrate that our analysis achieves the same precision as the best existing approach while drastically outperforming it in matters of analysis time.}
}

@techreport{KFM+11a,
Author = {Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury},
Title = {Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds.},
Year = {(2011).},
Number = {(#837),},
Month = {January},
Note = {hfalk, ESD, WCC},
Series = {20110126-report-837-kelter.pdf},
Address = {Dortmund / Germany},
Howpublished = {11-95 KFM+11a Dortmund},
Type = {Technical Report},
School = {TU Dortmund},
Institution = {Faculty of Computer Science},
Abstract = {In the domain of real-time systems, the analysis of the timing behavior of programs is crucial for guaranteeing the schedulability and thus the safeness of a system. Static analyses of the WCET (Worst-Case Execution Time) have proven to be a key element for timing analysis, as they provide safe upper bounds on a program's execution time. For single-core systems, industrial-strength WCET analyzers are already available, but up to now, only first proposals have been made to analyze the WCET in multicore systems, where the different cores may interfere during the access to shared TDMA-arbitrated resources. An important example for this are shared buses which connect the cores to a shared main memory. The time to gain access to the shared bus may vary significantly, depending on the used bus arbitration protocol and the access timings. In this report, we propose a new technique for analyzing the duration of accesses to shared buses. We implemented a prototype tool which uses the new analysis and tested it on a set of realworld benchmarks. Results demonstrate that our analysis achieves the same precision as the best existing approach while drastically outperforming it in matters of analysis time.}
}

@inproceedings{FF:2010c,
Author = {Alexander Finder and Goerschwin Fey},
Title = {Evaluating Debugging Algorithms from a Qualitative Perspective.},
Year = {(2010).},
Note = {gfey, CE},
Howpublished = {10-999 FF:2010c IWBP},
Booktitle = {<em>Int'l Workshop on Boolean Problems (IWSBP)</em>}
}

@inproceedings{FF:2010b,
Author = {Alexander Finder and Goerschwin Fey},
Title = {Evaluating Debugging Algorithms from a Qualitative Perspective.},
Year = {(2010).},
Note = {gfey, CE},
Howpublished = {10-999 FF:2010b FDL},
Booktitle = {<em>Forum on Specification and Design Languages (FDL)</em>}
}

@inproceedings{SFD:2010b,
Author = {André Sülflow and Goerschwin Fey and Rolf Drechsler},
Title = {Bounded Fault Tolerance Checking (Invited Talk).},
Year = {(2010).},
Note = {gfey, CE},
Howpublished = {10-999 SFD:2010b FDL},
Booktitle = {<em>Forum on Specification and Design Languages (FDL)</em>}
}

@inproceedings{SFD:2010,
Author = {André Sülflow and Goerschwin Fey and Rolf Drechsler},
Title = {Using QBF to Increase Accuracy of SAT-Based Debugging.},
Year = {(2010).},
Pages = {641-644},
Note = {gfey, CE},
Howpublished = {10-999 SFD:2010 ISCAS},
Booktitle = {<em>IEEE Int'l Symposium on Circuits and Systems (ISCAS)</em>}
}

@article{BYTZ10,
Author = {Cem Savas Bassoy, Svetlana Torgasin, Mei Yang and Karl-Heinz Zimmermann},
Title = {Accelerating Scalar-Product Based Sequence Alignment using Graphics Processor Units.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(2010).},
Volume = {<strong>61</strong>.},
Number = {(2),},
Pages = {117-125},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/s11265-009-0409-5},
Howpublished = {10-20 BYTZ10 JSPS},
Abstract = {Alignment is one of the basic operations in molecular biology to compare sequences. The most widely used methods for multiple sequence alignment include scalar-product based alignment of groups of sequences. We show that scalar-product based alignment algorithms can be significantly speeded up by general-purpose computing on a modern commonly available graphics card. Thus the huge computational power of graphics cards can be exploited to develop high performance solutions for multiple sequence alignment.}
}

@inproceedings{HAF+:2010,
Author = {Finn Haedicke and Bijan Alizadeh and Goerschwin Fey and Masahiro Fujita and Rolf Drechsler},
Title = {Polynomial Datapath Optimization using Constraint Solving and Formal Modelling.},
Year = {(2010).},
Pages = {756-761},
Note = {gfey, CE},
Howpublished = {10-999 HAF+:2010 ICCAD},
Booktitle = {<em>IEEE/ACM Int'l Conf. on CAD (ICCAD)</em>}
}

@unpublished{Fey:2010,
Author = {Goerschwin Fey (Organizer)},
Title = {Design Closure for Reliability.},
Year = {(2010).},
Note = {gfey, CE},
Howpublished = {10-999 Fey:2010 DAC},
Booktitle = {<em>Design Automation Conference (DAC)</em>}
}

@inproceedings{FSD:2010,
Author = {Goerschwin Fey and André Sülflow and Rolf Drechsler},
Title = {Towards Unifying Localization and Explanation for Automated Debugging.},
Year = {(2010).},
Pages = {3-8},
Note = {gfey, CE},
Howpublished = {10-999 FSD:2010 MTV},
Booktitle = {<em>International Workshop on Microprocessor Test and Verification (MTV)</em>}
}

@article{FSFD:2010,
Author = {Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler},
Title = {Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen.},
Journal = {<em>it - Information Technology</em>.},
Year = {(2010).},
Pages = {216-222},
Note = {gfey, CE},
Howpublished = {10-999 FSFD:2010 IT}
}

@article{FaLo10,
Author = {Heiko Falk and Paul Lokuciejewski},
Title = {A compiler framework for the reduction of worst-case execution times.},
Journal = {<em>the International Journal of Time-Critical Computing Systems (Real-Time Systems)</em>.},
Year = {(2010).},
Volume = {<strong>46</strong>.},
Number = {(2),},
Pages = {251-300},
Month = {October},
Note = {hfalk, ESD, WCC},
Publisher = {Springer:},
Series = {20100727-springer-rts-falk.pdf},
Isbn = {10.1007/s11241-019-09337-9},
Howpublished = {10-25 FaLo10 RTS},
Abstract = {The current practice to design software for real-time systems is tedious. There is almost no tool support that assists the designer in automatically deriving safe bounds of the worst-case execution time (WCET) of a system during code generation and in systematically optimizing code to reduce WCET.<br /> This article presents concepts and infrastructures for WCET-aware code generation and optimization techniques for WCET reduction. All together, they help to obtain code explicitly optimized for its worst-case timing, to automate large parts of the real-time software design flow, and to reduce costs of a real-time system by allowing to use tailored hardware.}
}

@article{MBWZ10,
Author = {Israel Marck Martinez-Perez, Wolfgang Brandt, Michael Wild and Karl-Heinz Zimmermann},
Title = {Bioinspired Parallel Algorithms for Maximum Clique Problem on FPGA Architectures.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(2010).},
Volume = {<strong>58</strong>.},
Number = {(2),},
Pages = {117-124},
Month = {February},
Note = {wbrandt, khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/s11265-008-0322-3},
Howpublished = {10-80 MBWZ10 JSPS},
Abstract = {The stickers model is a model of DNA computation that is computationally complete and universal. Many NP complete problems can be described by stickers programs that have polynomial runtime and are exponential in space. The stickers model can be viewed as a bit-vertically operating register machine. This makes it attractive for in silico implementation. This paper describes a stickers model for the maximum clique problem and its implementation by an FPGA architecture. The results show that the FPGA based algorithm is comparable with existing software algorithms for moderate problem sizes. More generally, the stickers model seems to be a well-suited programming model for dedicated hardware.}
}

@article{Zimm10,
Author = {Karl-Heinz Zimmermann},
Title = {Und, wie hoch ist Ihre Erd&ouml;s-Zahl?.},
Journal = {<em>Spektrum Magazin</em>.},
Year = {(2010).},
Note = {khzimmermann, AEG},
Publisher = {Technische Universit&auml;t Hamburg-Harburg:},
Howpublished = {10-95 Zimm10 Spektrum}
}

@article{SaZi10d,
Author = {Mehwish Saleemi and Karl-Heinz Zimmermann},
Title = {From ideals in polynomial rings to linear codes using Groebner bases.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2010).},
Volume = {<strong>65</strong>.},
Number = {(1),},
Pages = {41-54},
Month = {December},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Howpublished = {10-15 SaZi10d IJPAM},
Abstract = {In this paper, we investigate linear codes as ideals in the group algebra over an elementary abelian <em>p</em>-group. We provide a description of these codes in terms of Groebner bases and supply corresponding encoding and decoding procedures. In particular, we study generalizations of primitive Reed-Muller codes, construct their Groebner bases, and give their code parameters. Finally, we show that the class of codes studied contains an interesting family of linear codes. These codes have a designed Hamming distance and turn out to be superior to the primitive Reed-Muller codes in the non-binary case.}
}

@article{SaZi10c,
Author = {Mehwish Saleemi and Karl-Heinz Zimmermann},
Title = {Groebner bases for linear codes.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2010).},
Volume = {<strong>62</strong>.},
Number = {(4),},
Pages = {481-491},
Month = {August},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20100801-saleemi-ijpam.pdf},
Howpublished = {10-30 SaZi10c IJPAM},
Abstract = {Each linear code can be described by a binomial ideal given as the sum of a toric ideal and a non-prime ideal. In this paper, we show that each such binomial ideal has a very natural reduced Groebner basis which can be easily constructed from a systematic generator matrix of the code.}
}

@article{SaZi10b,
Author = {Mehwish Saleemi and Karl-Heinz Zimmermann},
Title = {Linear codes as binomial ideals.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2010).},
Volume = {<strong>61</strong>.},
Number = {(2),},
Pages = {147-156},
Month = {June},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20100601-saleemi-ijpam.pdf},
Howpublished = {10-50 SaZi10b IJPAM},
Abstract = {Recently, binary linear codes were associated with binomial ideals. We show that each linear code can be described by a binomial ideal given as the sum of a toric ideal and a non-prime ideal. We compute the Hilbert polynomials of the projective subschemes corresponding to the binomial ideal of a code and its toric subideal. Moreover, we study the minimal generators and Groebner bases of the binomial ideals of a linear code. The situation turns out to be quite similar to the case of toric ideals. For the binomial ideals of binary linear codes, the Graver bases, the universal Groebner bases, and the set of circuits are essentially equal.}
}

@article{SaZi10a,
Author = {Mehwish Saleemi and Karl-Heinz Zimmermann},
Title = {Groebner bases for a class of ideals in commutative polynomial rings.},
Journal = {<em>International Journal of Pure and Applied Mathematics (IJPAM)</em>.},
Year = {(2010).},
Volume = {<strong>58</strong>.},
Number = {(1),},
Pages = {1-9},
Month = {February},
Note = {khzimmermann, AEG},
Publisher = {AP:},
Series = {20100201-saleemi-ijpam.pdf},
Howpublished = {10-85 SaZi10a IJPAM},
Abstract = {We construct reduced Groebner bases for a certain class of ideals in commutative polynomial rings. A subclass of these ideals corresponds to the generalized Reed-Muller codes when considered in the quotient ring of the polynomial ring.}
}

@article{ReZi10a,
Author = {Oscar Mauricio Reyes and Karl-Heinz Zimmermann},
Title = {Permutation parity machines for neural cryptography.},
Journal = {<em>Physical Review E</em>.},
Year = {(2010).},
Volume = {<strong>81</strong>.},
Number = {(6),},
Month = {June},
Note = {khzimmermann, AEG},
Publisher = {American Physical Society:},
Isbn = {10.1103/PHYSREVE.81.066117},
Howpublished = {10-45 ReZi10a},
Abstract = {Recently, synchronization was proved for permutation parity machines, multilayer feed-forward neural networks proposed as a binary variant of the tree parity machines. This ability was already used in the case of tree parity machines to introduce a key-exchange protocol. In this paper, a protocol based on permutation parity machines is proposed and its performance against common attacks (simple, geometric, majority and genetic) is studied.}
}

@inproceedings{LPF+10,
Author = {Paul Lokuciejewski, Sascha Plazar, Heiko Falk, Peter Marwedel and Lothar Thiele},
Title = {Multi-Objective Exploration of Compiler Optimizations for Real-Time Systems.},
Year = {(2010).},
Pages = {115-122},
Month = {May},
Note = {hfalk, ESD, WCC},
Series = {20100506-isorc-lokuciejewski-falk.pdf},
Address = {Carmona / Spain},
Isbn = {10.1109/ISORC.2010.15},
Howpublished = {10-60 LFP+10 ISORC},
Booktitle = {<em>In Proceedings of the 13th International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC)</em>},
Abstract = {With the growing complexity of embedded systems software, high code quality can only be achieved using a compiler. Sophisticated compilers provide a vast spectrum of various optimizations to improve code aggressively w. r. t. different objective functions, e. g., average-case execution time (ACET) or code size. Due to the complex interactions between the optimizations, the choice for a promising sequence of code transformations is not trivial. Compiler developers address this problem by proposing standard optimization levels, e. g., O3 or Os. However, previous studies have shown that these standard levels often miss optimization potential or might even result in performance degradation.<br /> In this paper, we propose the first adaptive WCET-aware compiler framework for an automatic search of compiler optimization sequences which yield highly optimized code. Besides the objective functions ACET and code size, we consider the worst-case execution time (WCET) which is a crucial parameter for real-time systems. To find suitable trade-offs between these objectives, stochastic evolutionary multi-objective algorithms identifying Pareto optimal solutions are exploited. A comparison based on statistical performance assessments is performed which helps to determine the most suitable multi-objective optimizer. The effectiveness of our approach is demonstrated on real-life benchmarks showing that standard optimization levels can be significantly outperformed.}
}

@misc{MaFa10,
Author = {Peter Marwedel and Heiko Falk},
Title = {Reconciling compilers and timing analysis.},
Year = {(2010).},
Month = {April},
Note = {hfalk, ESD, WCC},
Series = {20100412-cpsweek-industrialworkshop-marwedel-falk.pdf},
Address = {Stockholm / Sweden},
Howpublished = {10-65 MaFa10 CPSWEEK},
Type = {Invited Talk at the CPSWEEK Industrial Workshop,}
}

@unpublished{DF:2010,
Author = {Rolf Drechsler and Goerschwin Fey},
Title = {Formal verification meets robustness checking - techniques and challenges (Tutorial).},
Year = {(2010).},
Note = {gfey, CE},
Howpublished = {10-999 DF:2010}
}

@inproceedings{FF:2010,
Author = {Stefan Frehse and Goerschwin Fey},
Title = {Kompositionelle Formale Robustheitsprüfung.},
Year = {(2010).},
Pages = {73-74},
Note = {gfey, CE},
Howpublished = {10-999 FF:2010 ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@inproceedings{FFSD:2010,
Author = {Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler},
Title = {RobuCheck: A Robustness Checker for Digital Circuits.},
Year = {(2010).},
Pages = {226-231},
Note = {gfey, CE},
Howpublished = {10-999 FFSD:2010 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{FFSD:2010b,
Author = {Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler},
Title = {RobuCheck: A Robustness Checker for Digital Circuits.},
Year = {(2010).},
Pages = {37-38},
Note = {gfey, CE},
Howpublished = {10-999 FFSD:2010b DYADEM},
Booktitle = {<em>Workshop on Dynamic Aspects in Dependability Model for Fault-Tolerant Systems (DYADEM-FTS)</em>}
}

@inproceedings{FFD:2010c,
Author = {Stefan Frehse and Goerschwin Fey and Rolf Drechsler},
Title = {A Better-Than-Worst-Case Robustness Measure.},
Year = {(2010).},
Note = {gfey, CE},
Howpublished = {10-999 FFD:2010c ITC},
Booktitle = {<em>Int'l Test Conference (ITC)</em>}
}

@inproceedings{FFD:2010,
Author = {Stefan Frehse and Goerschwin Fey and Rolf Drechsler},
Title = {A Better-Than-Worst-Case Robustness Measure.},
Year = {(2010).},
Pages = {78-83},
Note = {gfey, CE},
Howpublished = {10-999 FFD:2010 DDECS},
Booktitle = {<em>IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</em>}
}

@inproceedings{FFD:2010b,
Author = {Stefan Frehse and Goerschwin Fey and Rolf Drechsler},
Title = {A Better-Than-Worst-Case Robustness Measure.},
Year = {(2010).},
Pages = {19-24},
Note = {gfey, CE},
Howpublished = {10-999 FFD:2010b TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@article{EFG+:2010,
Author = {Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Rolf Drechsler},
Title = {MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.},
Journal = {<em>Journal of Electronic Testing: Theory and Applications (JETTA)</em>.},
Year = {(2010).},
Pages = {307-322},
Note = {gfey, CE},
Howpublished = {10-999 EFG+:2010 JETTA}
}

@article{ToZi10,
Author = {Svetlana Torgasin and Karl-Heinz Zimmermann},
Title = {Algorithm for thermodynamically based prediction of DNA/DNA crosshybridization.},
Journal = {<em>International Journal of Bioinformatics Research and Applications (IJBRA)</em>.},
Year = {(2010).},
Volume = {<strong>6</strong>.},
Number = {(1),},
Pages = {82-97},
Note = {khzimmermann, AEG},
Publisher = {Inderscience:},
Howpublished = {10-90 ToZi10 IJBRA},
Abstract = {A careful design of DNA strands is crucial for several biological applications such as microarray techniques, Polymerase Chain Reaction (PCR), and DNA computing. For this, the important criterion under laboratory conditions is the hybridisation energy of two DNA strands. During the last decade, a thermodynamic model was developed that allows for the calculation of the DNA/DNA hybridisation energy and recently also the cross-hybridisation energy of structural motifs. Employing this model a new algorithm for the secondary structure prediction of DNA/DNA cross-hybridisation complexes called HYBGRAPH is introduced. The method is based on Gibbs free energy minimisation and the paradigm of dynamic programming.}
}

@book{Kram10,
Author = {Wolfgang Kramper},
Title = {Simulation von Schwarmverhalten.},
Year = {(2010).},
Month = {April},
Note = {AEG},
Publisher = {Mensch & Buch:},
Howpublished = {10-70 Kram10 mbv}
}

@inproceedings{SFB+:2009,
Author = {André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler},
Title = {Increasing the Accuracy of SAT-based Debugging.},
Year = {(2009).},
Pages = {1326-1331},
Note = {gfey, CE},
Howpublished = {09-999 SFB+:2009 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{SFB+:2009b,
Author = {André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler},
Title = {Increasing the Accuracy of SAT-based Debugging.},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 SFB+:2009b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{SFD:2009,
Author = {André Sülflow and Goerschwin Fey and Rolf Drechsler},
Title = {Using QBF to Increase Accuracy of SAT-based Debugging.},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 SFD:2009 CFV},
Booktitle = {<em>Workshop on Constraints in Formal Verification (CFV)</em>}
}

@inproceedings{SWFD:2009,
Author = {André Sülflow and Robert Wille and Goerschwin Fey and Rolf Drechsler},
Title = {Evaluation of Cardinality Constraints on SMT-based Debugging.},
Year = {(2009).},
Pages = {298-303},
Note = {gfey, CE},
Howpublished = {09-999 SWFD:2009 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@inproceedings{SFFD:2009,
Author = {André Sülflow and Stefan Frehse and Goerschwin Fey and Rolf Drechsler},
Title = {Anwendungsbezogene Analyse der Robustheit von digitalen Schaltungen.},
Year = {(2009).},
Pages = {45-52},
Note = {gfey, CE},
Howpublished = {09-999 SFFD:2009 ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@inproceedings{SKF+:2009,
Author = {André Sülflow and Ulrich Kühne and Goerschwin Fey and Daniel Große and Rolf Drechsler},
Title = {WoLFram - A Word Level Framework for Formal Verification.},
Year = {(2009).},
Pages = {11-17},
Note = {gfey, CE},
Howpublished = {09-999 SKF+:2009 RSP},
Booktitle = {<em>IEEE/IFIP Int'l Symposium on Rapid System Prototyping (RSP)</em>}
}

@unpublished{BDEF:2009,
Author = {Dominique Borrione and Rolf Drechsler and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey},
Title = {Formal and Semi-formal Methods for Correctness and Robustness (Tutorial).},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 BDEF:2009}
}

@article{RKF+:2009,
Author = {Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke},
Title = {Advanced Verification by Automatic Property Generation.},
Journal = {<em>IET Computers and Digital Techniques</em>.},
Year = {(2009).},
Pages = {338-353},
Note = {gfey, CE},
Howpublished = {09-999 RKF+:2009 IETCDT}
}

@inproceedings{Fey:2009,
Author = {Goerschwin Fey},
Title = {Deterministic Algorithms for ATPG under Leakage Constraints.},
Year = {(2009).},
Pages = {313-316},
Note = {gfey, CE},
Howpublished = {09-999 Fey:2009 ATS},
Booktitle = {<em>Asian Test Symposium (ATS)</em>}
}

@inproceedings{Fey:2009b,
Author = {Goerschwin Fey},
Title = {Algorithms for ATPG under Leakage Constraints.},
Year = {(2009).},
Pages = {91-96},
Note = {gfey, CE},
Howpublished = {09-999 Fey:2009b TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{FSD:2009,
Author = {Goerschwin Fey and André Sülflow and Rolf Drechsler},
Title = {Computing Bounds for Fault Tolerance using Formal Techniques.},
Year = {(2009).},
Pages = {190-195},
Note = {gfey, CE},
Howpublished = {09-999 FSD:2009 DAC},
Booktitle = {<em>Design Automation Conference (DAC)</em>}
}

@inproceedings{Falk09c,
Author = {Heiko Falk},
Title = {WCET-aware Register Allocation based on Graph Coloring.},
Year = {(2009).},
Pages = {726-731},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20090730-dac-falk.pdf},
Address = {San Francisco / USA},
Isbn = {10.1145/1629911.1630100},
Howpublished = {09-55 Falk09c DAC},
Booktitle = {<em>In Proceedings of the 46th Design Automation Conference (DAC)</em>},
Abstract = {Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is register allocation. Many compilers heuristically decide when and where to spill a register to memory, without having a clear understanding of the impact of such spill code on a program's run time.<br /> This paper extends a graph coloring register allocator such that it uses precise worst-case execution time (WCET) models. Using this WCET timing data, the compiler tries to avoid spill code generation along the critical path defining a program’s WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware register allocator. Our results underline the effectiveness of the proposed techniques. For a total of 46 realistic benchmarks, we reduced WCETs by 31.2% on average. Additionally, the runtimes of our WCET-aware register allocator still remain acceptable.}
}

@misc{Falk09a,
Author = {Heiko Falk},
Title = {Compiler Techniques for hard Real-Time Systems (in German).},
Year = {(2009).},
Month = {April},
Note = {hfalk, ESD, WCC},
Address = {Schloss Dagstuhl / Germany},
Howpublished = {09-70 Falk09a GIBU},
Type = {Invited Talk at the Annual Meeting of University Professors of the German Society of Informatics (GIBU),}
}

@proceedings{Falk09b,
Author = {Heiko Falk (Ed.)},
Title = {Proceedings of the 12th International Workshop on Software & Compilers for Embedded Systems (SCOPES).},
Year = {(2009).},
Month = {April},
Note = {hfalk, ESD},
Publisher = {ACM:},
Address = {Nice / France},
Howpublished = {09-65 Falk09b SCOPES},
Url = {http://www.scopesconf.org/scopes-09}
}

@inproceedings{FaKl09,
Author = {Heiko Falk and Jan C. Kleinsorge},
Title = {Optimal Static WCET-aware Scratchpad Allocation of Program Code.},
Year = {(2009).},
Pages = {732-737},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20090730-dac-falk-kleinsorge.pdf},
Address = {San Francisco / USA},
Isbn = {10.1145/1629911.1630101},
Howpublished = {09-50 FaKl09 DAC},
Booktitle = {<em>In Proceedings of the 46th Design Automation Conference (DAC)</em>},
Abstract = {Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictability is highly undesired especially when designing real-time systems where the worst-case execution time (WCET) is one of the key metrics. Scratchpad memories (SPMs) have proven to be a fully predictable alternative to caches. In contrast to caches, however, SPMs require dedicated compiler support.<br /> This paper presents an optimal static SPM allocation algorithm for program code. It minimizes WCETs by placing the most beneficial parts of a program's code in an SPM. Our results underline the effectiveness of the proposed techniques. For a total of 73 realistic benchmarks, we reduced WCETs on average by 7.4% up to 40%. Additionally, the run times of our ILP-based SPM allocator are negligible.}
}

@article{MaZi09,
Author = {Israel Marck Martinez-Perez and Karl-Heinz Zimmermann},
Title = {Parallel bioinspired algorithms for NP complete graph problems.},
Journal = {<em>Journal of Parallel and Distributed Computing (JPDC)</em>.},
Year = {(2009).},
Volume = {<strong>69</strong>.},
Number = {(3),},
Pages = {221-229},
Month = {March},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/j.jpdc.2008.06.014},
Howpublished = {09-85 MaZi09 JPDC},
Abstract = {It is no longer believed that DNA computing will outperform digital computers when it comes to the computation of intractable problems. In this paper, we emphasise the in silico implementation of DNA-inspired algorithms as the only way to compete with other algorithms for solving NP-complete problems. For this, we provide sticker algorithms for some of the most representative NP-complete graph problems. The simple data structures and bit-vertical operations make them suitable for some parallel architectures. The parallel algorithms might solve either moderate-size problems in an exact manner or, when combined with a heuristic, large problems in polynomial time.}
}

@article{MIZ09b,
Author = {Israel Marck Martinez-Perez, Karl-Heinz Zimmermann and Zoya Ignatova},
Title = {An autonomous DNA model for finite state automata.},
Journal = {<em>International Journal of Bioinformatics Research and Applications (IJBRA)</em>.},
Year = {(2009).},
Volume = {<strong>5</strong>.},
Number = {(1),},
Pages = {81-96},
Note = {khzimmermann, AEG},
Publisher = {Inderscience:},
Isbn = {10.1504/IJBRA.2009.022465},
Howpublished = {09-90 MIZ09b IJBRA},
Abstract = {In this paper we introduce an autonomous DNA model for finite state automata. This model called sticker automaton model is based on the hybridisation of single stranded DNA molecules (stickers) encoding transition rules and input data. The computation is carried out in an autonomous manner by one enzyme which allows us to determine whether a resulting double-stranded DNA molecule belongs to the automaton's language or not.}
}

@article{MIZ09a,
Author = {Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann},
Title = {Exploiting the Features of the Finite State Automata for Biomolecular Computing.},
Journal = {<em>Journal on Recent Patents on DNA & Gene Sequences</em>.},
Year = {(2009).},
Volume = {<strong>3</strong>.},
Number = {(2),},
Pages = {130-138},
Note = {khzimmermann, AEG},
Publisher = {Bentham Science:},
Isbn = {10.2174/187221509788654142},
Howpublished = {09-95 MIZ09a RPDNA},
Abstract = {Here, we review patents that have emerged in the field of DNA-based computing focusing thereby on the discoveries using the concept of molecular finite state automata. A finite state automaton, operating on a finite sequence of symbols and converting information from one to another, provides a basis for developing molecular-scale autonomous programmable models of biomolecular computation at cellular level. We also provide a brief overview on inventions which methodologically support the DNA-based computational approach.}
}

@inproceedings{ReZi09,
Author = {Oscar Mauricio Reyes Torres and Karl-Heinz Zimmermann},
Title = {Key exchange protocol using permutation parity machines.},
Year = {(2009).},
Pages = {496-501},
Month = {October},
Note = {khzimmermann, AEG},
Address = {Madeira / Portugal},
Howpublished = {09-45 ReZi09 IJCCI},
Booktitle = {<em>In Proceedings of the International Joint Conference on Computational Intelligence (IJCCI)</em>}
}

@article{RKZ09,
Author = {Oscar Mauricio Reyes Torres, I. Kopitzke and Karl-Heinz Zimmermann},
Title = {Permutation parity machines for neural synchronization.},
Journal = {<em>Journal of Physics A: Mathematical and Theoretical</em>.},
Year = {(2009).},
Volume = {<strong>42</strong>.},
Number = {(19),},
Month = {April},
Note = {khzimmermann, AEG},
Publisher = {IOP Publishing:},
Isbn = {10.1088/1751-8113/42/19/195002},
Howpublished = {09-75 RKZ09 JPA},
Abstract = {Synchronization of neural networks has been studied in recent years as an alternative to cryptographic applications such as the realization of symmetric key exchange protocols. This paper presents a first view of the so-called permutation parity machine, an artificial neural network proposed as a binary variant of the tree parity machine. The dynamics of the synchronization process by mutual learning between permutation parity machines is analytically studied and the results are compared with those of tree parity machines. It will turn out that for neural synchronization, permutation parity machines form a viable alternative to tree parity machines.}
}

@inproceedings{LCFM09,
Author = {Paul Lokuciejewski, Daniel Cordes, Heiko Falk and Peter Marwedel},
Title = {A Fast and Precise Static Loop Analysis based on Abstract Interpretation, Program Slicing and Polytope Models.},
Year = {(2009).},
Pages = {136-146},
Month = {March},
Note = {hfalk, ESD, WCC},
Series = {20090324-cgo-lokuciejewski-falk.pdf},
Address = {Seattle / USA},
Isbn = {10.1109/CGO.2009.17},
Howpublished = {09-80 LCFM09 CGO},
Booktitle = {<em>In Proceedings of the International Symposium on Code Generation and Optimization (CGO)</em>},
Abstract = {A static loop analysis is a program analysis computing loop iteration counts. This information is crucial for different fields of applications. In the domain of compilers, the knowledge about loop iterations can be exploited for aggressive loop optimizations like Loop Unrolling. A loop analyzer also provides static information about code execution frequencies which can assist feedback-directed optimizations. Another prominent application is the static worst-case execution time (WCET) analysis which relies on a safe approximation of loop iteration counts.<br /> In this paper, we propose a framework for a static loop analysis based on Abstract Interpretation, a theory of a sound approximation of program semantics. To accelerate the analysis, we preprocess the analyzed code using Program Slicing, a technique that removes statements irrelevant for the loop analysis. In addition, we introduce a novel polytope-based loop evaluation that further significantly reduces the analysis time. The efficiency of our loop analyzer is evaluated on a large number of benchmarks. Results show that 99% of the considered loops could be successfully analyzed in an acceptable amount of time. This study points out that our methodology is best suited for real-world problems.}
}

@incollection{WFG+:2009,
Author = {Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler},
Title = {SWORD: A SAT like prover using word level information.},
Year = {(2009).},
Pages = {175-192},
Note = {gfey, CE},
Howpublished = {09-999 WFG+:2009 {VLSI-SOC: ADVANCED TOPICS ON SYSTEMS ON A CHIP}},
Booktitle = {<em>VLSI-SoC: Advanced Topics on Systems on a Chip</em>}
}

@unpublished{DF:2009,
Author = {Rolf Drechsler and Goerschwin Fey},
Title = {Formale Verifikation und Robustheit (Tutorial).},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 DF:2009}
}

@article{DEFT:2009b,
Author = {Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille},
Title = {Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern.},
Journal = {<em>it - Information Technology</em>.},
Year = {(2009).},
Pages = {102-111},
Note = {gfey, CE},
Howpublished = {09-999 DEFT:2009b IT}
}

@book{DEFT:2009,
Author = {Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille},
Title = {Test Pattern Generation using Boolean Proof Engines.},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 DEFT:2009}
}

@inproceedings{DEFT:2009c,
Author = {Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille},
Title = {SAT-based Automatic Test Pattern Generation.},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 DEFT:2009c {EVOLUTIONARY TEST GENERATION DAGSTUHL-SEMINAR}},
Booktitle = {<em>Evolutionary Test Generation Dagstuhl-Seminar</em>}
}

@inproceedings{FFSD:2009,
Author = {Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler},
Title = {Robustness Check for Multiple Faults using Formal Techniques.},
Year = {(2009).},
Pages = {85-90},
Note = {gfey, CE},
Howpublished = {09-999 FFSD:2009 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{FFSD:2009b,
Author = {Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler},
Title = {Robustness Check for Multiple Faults using Formal Techniques.},
Year = {(2009).},
Note = {gfey, CE},
Howpublished = {09-999 FFSD:2009b CFV},
Booktitle = {<em>Workshop on Constraints in Formal Verification (CFV)</em>}
}

@inproceedings{NTF+:2009,
Author = {Toru Nakura and Yutaro Tatemura and Goerschwin Fey and Makoto Ikeda and Satoshi Komatsu and Kunihiro Asada},
Title = {SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults.},
Year = {(2009).},
Pages = {643-647},
Note = {gfey, CE},
Howpublished = {09-999 NTF+:2009 ECCTD},
Booktitle = {<em>European Conference on Circuit Theory and Design (ECCTD)</em>}
}

@inproceedings{SFBD:2008,
Author = {André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler},
Title = {Using Unsatisfiable Cores to Debug Multiple Design Errors.},
Year = {(2008).},
Pages = {77-82},
Note = {gfey, CE},
Howpublished = {08-999 SFBD:2008 GLS},
Booktitle = {<em>Great Lakes Symp. VLSI (GLS)</em>}
}

@inproceedings{SFBD:2008b,
Author = {André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler},
Title = {Debugging Design Errors by Using Unsatisfiable Cores.},
Year = {(2008).},
Pages = {159-168},
Note = {gfey, CE},
Isbn = {ISBN},
Howpublished = {08-999 SFBD:2008b MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>},
Doi = {DOI},
Keywords = {keywords}
}

@inproceedings{SFD:2008,
Author = {André Sülflow and Goerschwin Fey and Rolf Drechsler},
Title = {Experimental Studies on SMT-based Debugging.},
Year = {(2008).},
Pages = {93-98},
Note = {gfey, CE},
Howpublished = {08-999 SFD:2008 WRTLT},
Booktitle = {<em>IEEE Workshop on RTL and High Level Testing (WRTLT)</em>}
}

@inproceedings{SFF+:2008,
Author = {André Sülflow and Goerschwin Fey and Stefan Frehse and Ulrich Kühne and Rolf Drechsler},
Title = {Computing Bounds for Fault Tolerance using Formal Techniques.},
Year = {(2008).},
Note = {gfey, CE},
Howpublished = {08-999 SFF+:2008 DRV},
Booktitle = {<em>Workshop on Design for Reliability and Variability (DRV)</em>}
}

@inproceedings{RKF+:2008,
Author = {Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke},
Title = {Automatic Generation of Complex Properties for Hardware Designs.},
Year = {(2008).},
Pages = {545-548},
Note = {gfey, CE},
Howpublished = {08-999 RKF+:2008 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{RKR+:2008,
Author = {Frank Rogin and Thomas Klotz and Steffen Rülke and Goerschwin Fey and Rolf Drechsler},
Title = {Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs.},
Year = {(2008).},
Note = {gfey, CE},
Howpublished = {08-999 RKR+:2008 DASS},
Booktitle = {<em>Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)</em>}
}

@inproceedings{FSF+:2008,
Author = {Goerschwin Fey and André Sülflow and Stefan Frehse and Ulrich Kühne and Rolf Drechsler},
Title = {Formaler Nachweis der Fehlertoleranz von Schaltkreisen.},
Year = {(2008).},
Pages = {75-82},
Note = {gfey, CE},
Howpublished = {08-999 FSF+:2008 ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@article{FBCD:2008,
Author = {Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler},
Title = {On the Construction of Small Fully Testable Circuits with Low Depth.},
Journal = {<em>Microprocessors and Microsystems (MICPRO)</em>.},
Year = {(2008).},
Pages = {263-269},
Note = {gfey, CE},
Howpublished = {08-999 FBCD:2008 MICPRO}
}

@inproceedings{FD:2008c,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Synthesis for Detection of Transient Faults.},
Year = {(2008).},
Pages = {161-166},
Note = {gfey, CE},
Howpublished = {08-999 FD:2008c {IEICE WORKSHOP ON DEPENDABLE COMPUTING}},
Booktitle = {<em>IEICE Workshop on Dependable Computing</em>}
}

@inproceedings{FD:2008,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {A Basis for Formal Robustness Checking.},
Year = {(2008).},
Pages = {784-789},
Note = {gfey, CE},
Howpublished = {08-999 FD:2008 ISQED},
Booktitle = {<em>Int'l Symposium on Quality Electronic Design (ISQED)</em>}
}

@book{FD:2008b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Robustness and Usability in Modern Design Flows.},
Year = {(2008).},
Note = {gfey, CE},
Howpublished = {08-999 FD:2008b}
}

@inproceedings{FKFF:2008,
Author = {Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita},
Title = {Targeting Leakage Constraints during ATPG.},
Year = {(2008).},
Pages = {225-230},
Note = {gfey, CE},
Howpublished = {08-999 FKFF:2008 ATS},
Booktitle = {<em>Asian Test Symposium (ATS)</em>}
}

@inproceedings{FKFF:2008b,
Author = {Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita},
Title = {Targeting Leakage Constraints during ATPG.},
Year = {(2008).},
Note = {gfey, CE},
Howpublished = {08-999 FKFF:2008b SDD},
Booktitle = {<em>IEEE Int'l Workshop on Silicon Debug and Diagnosis (SDD)</em>}
}

@article{FSBD:2008,
Author = {Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler},
Title = {Automatic Fault Localization for Property Checking.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2008).},
Pages = {1138-1149},
Note = {gfey, CE},
Howpublished = {08-999 FSBD:2008 TCAD}
}

@article{FSBD:2008_long,
Author = {Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler},
Title = {Automatic Fault Localization for Property Checking.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2008).},
Pages = {1138-1149},
Note = {gfey, CE},
Howpublished = {08-999 FSBD:2008_long TCAD}
}

@misc{Falk08b,
Author = {Heiko Falk},
Title = {Memory-architecture aware compilation.},
Year = {(2008).},
Month = {November},
Note = {hfalk, ESD},
Address = {Dresden / Germany},
Howpublished = {08-55 Falk08b TUD},
Type = {Invited Talk at the Technical University Dresden, Faculty of Computer Science,}
}

@proceedings{Falk08a,
Author = {Heiko Falk (Ed.)},
Title = {Proceedings of the 11th International Workshop on Software & Compilers for Embedded Systems (SCOPES).},
Year = {(2008).},
Month = {March},
Note = {hfalk, ESD},
Publisher = {ACM:},
Address = {Munich / Germany},
Howpublished = {08-90 Falk08a SCOPES},
Url = {http://www.scopesconf.org/scopes-08}
}

@inproceedings{LFM08,
Author = {Paul Lokuciejewski, Heiko Falk and Peter Marwedel},
Title = {WCET-driven Cache-based Procedure Positioning Optimizations.},
Year = {(2008).},
Pages = {321-330},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20080704-ecrts-lokuciejewski-falk.pdf},
Address = {Prague / Czech Republic},
Isbn = {10.1109/ECRTS.2008.20},
Howpublished = {08-75 LFM08 ECRTS},
Booktitle = {<em>In Proceedings of the 20th Euromicro Conference on Real-Time Systems (ECRTS)</em>},
Abstract = {Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other frequently in the memory avoids overlapping of cache lines and thus decreases the number of cache conflict misses. In standard literature, these positioning techniques are guided by execution profile data and focus on an improved average-case performance.<br /> We present two novel positioning optimizations driven by worst-case execution time (WCET) information to effectively minimize the program’s worst-case behavior. WCET reductions by 10% on average are achieved. Moreover, a combination of positioning and the WCET-driven Procedure Cloning optimization proposed in [14] is presented improving the WCET analysis by 36% on average.}
}

@inproceedings{LFMT08,
Author = {Paul Lokuciejewski, Heiko Falk, Peter Marwedel and Henrik Theiling},
Title = {WCET-Driven, Code-Size Critical Procedure Cloning.},
Year = {(2008).},
Pages = {21-30},
Month = {March},
Note = {hfalk, ESD, WCC},
Series = {20080314-scopes-lokuciejewski-falk.pdf},
Address = {Munich / Germany},
Howpublished = {08-95 LFMT08 SCOPES},
Booktitle = {<em>In Proceedings of the 11th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {In the domain of the worst-case execution time (WCET) analysis, loops are an inherent source of unpredictability and loss of precision since the determination of tight and safe information on the number of loop iterations is a difficult task. In particular, data-dependent loops whose iteration counts depend on function parameters can not be precisely handled by a timing analysis. Procedure Cloning can be exploited to make these loops explicit within the source code allowing a highly precise WCET analysis.<br /> In this paper we extend the standard Procedure Cloning optimization by WCET-aware concepts with the objective to improve the tightness of the WCET estimation. Our novel approach is driven by WCET information which successively eliminates code structures leading to overestimated timing results, thus making the code more suitable for the analysis. In addition, the code size increase during the optimization is monitored and large increases are avoided.<br /> The effectiveness of our optimization is shown by tests on real-world benchmarks. After performing our optimization, the estimated WCET is reduced by up to 64.2% while the employed code transformations yield an additional code size increase of 22.6% on average. In contrast, the average-case performance being the original objective of Procedure Cloning showed a slight decrease.}
}

@misc{MaFa08b,
Author = {Peter Marwedel and Heiko Falk},
Title = {Memory-architecture aware compilation.},
Year = {(2008).},
Month = {September},
Note = {hfalk, ESD, WCC},
Series = {20080910-artist2-summerschool-marwedel-falk.pdf},
Address = {Autrans / France},
Howpublished = {08-60 MaFa08b ARTIST},
Url = {http://www.artist-embedded.org/docs/Events/2008/Autrans/Videos/Peter_Marwedel_and_Heiko_Falk},
Type = {Lecture at the <a href="http://www.artist-embedded.org/artist/ARTIST2-Summer-School-2008.html" target="_blank">ARTIST2 Summer School 2008 in Europe</a>,}
}

@misc{MaFa08a,
Author = {Peter Marwedel and Heiko Falk},
Title = {Embedded Systems - with Emphasis on the Exploitation of the Memory Hierarchy.},
Year = {(2008).},
Month = {August},
Note = {hfalk, ESD},
Address = {Seoul / South Korea},
Howpublished = {08-65 MaFa08a AIIT},
Type = {Full-week Tutorial at the Advanced Institute of Information Technology (AIIT),}
}

@inproceedings{WFM+:2008,
Author = {Robert Wille and Goerschwin Fey and Marc Messing and Gerhard Angst and Lothar Linhard and Rolf Drechsler},
Title = {Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.},
Year = {(2008).},
Pages = {542-549},
Note = {gfey, CE},
Howpublished = {08-999 WFM+:2008 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@article{DEF+:2008,
Author = {Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Daniel Tille},
Title = {On Acceleration of SAT-based ATPG for Industrial Designs.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2008).},
Pages = {1329-1333},
Note = {gfey, CE},
Howpublished = {08-999 DEF+:2008 TCAD}
}

@book{MIZ08,
Author = {Zoya Ignatova, Israel Marck Martinez-Perez and Karl-Heinz Zimmermann},
Title = {DNA Computing Models.},
Year = {(2008).},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/978-0-387-73637-2},
Howpublished = {08-70 MIZ08 Springer},
Abstract = {Sir Francis Crick would undoubtedly be at the front of the line ordering this fascinating book. Being one of the discoverers of DNA, he would be amazed at how his work has been applied to mankind's most important invention, the computer. DNA contains the genetic instructions for the biological development of cellular life forms or viruses. DNA computing uses DNA as a substrate for storing information, while molecular biological operations are used to manipulate this information.<br /> DNA Computing Models begins with a comprehensive introduction to the field of DNA computing. This book emphasizes computational methods to tackle central problems of DNA computing, such as controlling living cells, building patterns, and generating nanomachines. DNA Computing Models presents laboratory-scale human-operated models of computation, including a description of the first experiment of DNA computation conducted by Adleman in 1994. It provides molecular-scale autonomous models of computation and addresses the design of computational devices working in living cells. It also addresses the important problem of proper word design for DNA computing.<br /> DNA Computing Models is designed for researchers and advanced-level students in computers science, bioengineering and molecular biology as a reference or secondary text book. This book is also suitable for practitioners in industry.}
}

@inproceedings{SFD:2007,
Author = {André Sülflow and Goerschwin Fey and Rolf Drechsler},
Title = {Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 SFD:2007 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{SVW07,
Author = {Bj&ouml;rn Saballus, Markus Volkmer and Sebastian Wallner},
Title = {Secure Group Communication in Ad-Hoc Networks using Tree Parity Machines.},
Year = {(2007).},
Month = {March},
Note = {AEG},
Address = {Bern / Switzerland},
Howpublished = {07-95 SVW07 WMAN},
Booktitle = {<em>In Proceedings of the 4th Workshop on Mobile Ad-Hoc Networks (WMAN)</em>},
Abstract = {A fundamental building block of secure group communication is the establishment of a common group key. This can be divided into key agreement and key distribution. Common group key agreement protocols are based on the Diffie-Hellman (DH) key exchange and extend it to groups. Group key distribution protocols are centralized approaches which make use of one or more special key servers. In contrast to these approaches, we present a protocol which makes use of the Tree Parity Machine key exchange between multiple parties. It does not need a centralized server and therefore is especially suitable for ad-hoc networks of any kind.}
}

@book{GFD:2007,
Author = {Daniel Große and Goerschwin Fey and Rolf Drechsler (editors)},
Title = {SATRIX - Algorithmen für Boolesche Erfüllbarkeit.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 GFD:2007}
}

@inproceedings{TFD:2007,
Author = {Daniel Tille and Goerschwin Fey and Rolf Drechsler},
Title = {Instance Generation for SAT-based ATPG.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 TFD:2007 DDECS_WS},
Booktitle = {<em>IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS)</em>}
}

@inproceedings{TEF+:2007,
Author = {Daniel Tille and Stephan Eggersglüß and Görschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel},
Title = {Studies on Integrating SAT-based ATPG in an Industrial Environment.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 TEF+:2007 TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@incollection{Fey:2007,
Author = {Goerschwin Fey},
Title = {Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques.},
Year = {(2007).},
Pages = {29-38},
Note = {gfey, CE},
Howpublished = {07-999 Fey:2007 {AUSGEZEICHNETE INFORMATIKDISSERTATIONEN 2006}},
Booktitle = {<em>Ausgezeichnete Informatikdissertationen 2006</em>}
}

@inproceedings{FBCD:2007,
Author = {Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler},
Title = {On the Construction of Small Fully Testable Circuits with Low Depth.},
Year = {(2007).},
Pages = {563-569},
Note = {gfey, CE},
Howpublished = {07-999 FBCD:2007 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{FGE+:2007,
Author = {Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Robert Wille and Rolf Drechsler},
Title = {Formal Verification on the Word Level using SAT-like Proof Techniques.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 FGE+:2007 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{FD:2007b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Formal Robustness Checking.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 FD:2007b CFV},
Booktitle = {<em>Workshop on Constraints in Formal Verification (CFV)</em>}
}

@inproceedings{FD:2007,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Ein formaler Ansatz zum Robustheitsnachweis.},
Year = {(2007).},
Pages = {101-108},
Note = {gfey, CE},
Howpublished = {07-999 FD:2007 ZUE},
Booktitle = {<em>GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)</em>}
}

@inproceedings{FWD:2007,
Author = {Goerschwin Fey and Tim Warode and Rolf Drechsler},
Title = {Using Structural Learning Techniques in SAT-based ATPG.},
Year = {(2007).},
Pages = {69-74},
Note = {gfey, CE},
Howpublished = {07-999 FWD:2007 VLSIDC},
Booktitle = {<em>VLSI Design Conference</em>}
}

@proceedings{FaMa07,
Author = {Heiko Falk and Peter Marwedel (Eds.)},
Title = {Proceedings of the 10th International Workshop on Software & Compilers for Embedded Systems (SCOPES).},
Year = {(2007).},
Month = {April},
Note = {hfalk, ESD},
Publisher = {ACM:},
Address = {Nice / France},
Howpublished = {07-80 FaMa07 SCOPES},
Url = {http://www.scopesconf.org/scopes-07}
}

@inproceedings{FPT07,
Author = {Heiko Falk, Sascha Plazar and Henrik Theiling},
Title = {Compile-Time Decided Instruction Cache Locking Using Worst-Case Execution Paths.},
Year = {(2007).},
Pages = {143-148},
Month = {September},
Note = {hfalk, ESD, WCC},
Series = {20071002-codes_isss-falk-plazar.pdf},
Address = {Salzburg / Austria},
Isbn = {10.1145/1289816.1289853},
Howpublished = {07-40 FPT07 CODES+ISSS},
Booktitle = {<em>In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)</em>},
Abstract = {Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability is highly undesired for real-time systems. The Worst-Case Execution Time (WCET) of a software running on an embedded processor is one of the most important metrics during real-time system design. The WCET depends to a large extent on the total amount of time spent for memory accesses. In the presence of caches, WCET analysis must always assume a memory access to be a cache miss if it can not be guaranteed that it is a hit. Hence, WCETs for cached systems are imprecise due to the overestimation caused by the caches.<br /> Modern caches can be controlled by software. The software can load parts of its code or of its data into the cache and lock the cache afterwards. Cache locking prevents the cache's contents from being flushed by deactivating the replacement. A locked cache is highly predictable and leads to very precise WCET estimates, because the uncertainty caused by the replacement strategy is eliminated completely.<br /> This paper presents techniques exploring the lockdown of instruction caches at compile-time to minimize WCETs. In contrast to the current state of the art in the area of cache locking, our techniques explicitly take the worst-case execution path into account during each step of the optimization procedure. This way, we can make sure that always those parts of the code are locked in the I-cache that lead to the highest WCET reduction. The results demonstrate that WCET reductions from 54% up to 73% can be achieved with an acceptable amount of CPU seconds required for the optimization and WCET analyses themselves.}
}

@phdthesis{Martinez07,
Author = {Israel Marck Martinez-Perez},
Title = {Biomolecular Computing Models for Graph Problems and Finite State Automata.},
Year = {(2007).},
Month = {December},
Note = {AEG},
Address = {Hamburg / Germany},
Howpublished = {07-30 Martinez07 PhD},
Type = {Ph.D. Thesis.},
School = {Hamburg University of Technology},
Institution = {School of Electrical Engineering, Computer Science and Mathematics}
}

@article{MIZ07,
Author = {Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann},
Title = {Computational genes: a tool for molecular diagnosis and therapy of aberrant mutational phenotype.},
Journal = {<em>BMC Bioinformatics</em>.},
Year = {(2007).},
Volume = {<strong>8</strong>.},
Number = {(365),},
Month = {September},
Note = {khzimmermann, AEG},
Publisher = {BioMed Central:},
Isbn = {10.1186/1471-2105-8-365},
Howpublished = {07-65 MIZ07 BMCBio}
}

@misc{ZIM07,
Author = {Karl-Heinz Zimmermann, Zoya Ignatova and Israel Marck Martinez-Perez},
Title = {Rechengen.},
Year = {(2007).},
Month = {September},
Note = {khzimmermann, AEG},
Address = {Munich / Germany},
Howpublished = {07-60 ZIM07 Patent},
Url = {https://register.dpma.de/DPMAregister/pat/register?AKZ=1020060090004},
Type = {German Patent No. DE102006009000B3,}
}

@inproceedings{LFSM07,
Author = {Paul Lokuciejewski, Heiko Falk, Martin Schwarzer and Peter Marwedel},
Title = {Tighter WCET Estimates by Procedure Cloning.},
Year = {(2007).},
Pages = {27-32},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20070703-wcet-lokuciejewski-falk.pdf},
Address = {Pisa / Italy},
Howpublished = {07-70 LFSM07 WCET},
Booktitle = {<em>In Proceedings of the 7th International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {Embedded software spends most of its execution time in loops. To allow a precise static WCET analysis, each loop iteration should, in theory, be represented by an individual calling context. However, due to the enormous analysis times of real-world applications, this approach is not feasible and requires a reduction of the analysis complexity by limiting the number of considered contexts. This restricted timing analysis results in imprecise WCET estimates. In particular, data-dependent loops with iteration counts depending on function parameters cannot be precisely analyzed. In order to reduce the number of contexts that must be implicitly considered, causing an increase in analysis time, we apply the standard compiler optimization procedure cloning which improves the program's predictability by making loops explicit and thus allowing a precise annotation of loop bounds. The result is a tight WCET estimation within a reduced analysis time. Our results indicate that reductions of the WCET between 12% and 95% were achieved for real-world benchmarks. In contrast, the reduction of the simulated program execution time remained marginal with only 3%. As will be also shown, this optimization only produces a small overhead for the WCET analysis.}
}

@inproceedings{LFS+07,
Author = {Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel and Henrik Theiling},
Title = {Influence of Procedure Cloning on WCET Prediction.},
Year = {(2007).},
Pages = {137-142},
Month = {September},
Note = {hfalk, ESD, WCC},
Series = {20071002-codes_isss-lokuciejewski-falk.pdf},
Address = {Salzburg / Austria},
Isbn = {10.1145/1289816.1289852},
Howpublished = {07-45 LFS+07 CODES+ISSS},
Booktitle = {<em>In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)</em>},
Abstract = {For the worst-case execution time (WCET) analysis, especially loops are an inherent source of unpredictability and loss of precision. This is caused by the difficulty to obtain safe and tight information on the number of iterations executed by a loop in the worst case. In particular, data-dependent loops whose iteration counts depend on function parameters are extremely difficult to analyze precisely. Procedure cloning helps by making such data-dependent loops explicit within the source code, thus making them accessible for high-precision WCET analyses.<br /> This paper presents the effect of procedure cloning applied at the source-code level on worst-case execution time. The optimization generates specialized versions of functions being called with constant values as arguments. In standard literature, it is used to enable further optimizations like constant propagation within functions and to reduce calling overhead.<br /> We show that procedure cloning for WCET minimization leads to significant improvements. Reductions of the WCET from 12% up to 95% were measured for real-life benchmarks. These results demonstrate that procedure cloning improves analyzability and predictability of real-time applications dramatically. In contrast, average-case performance as the criterion procedure cloning was developed for is reduced by only 3% at most. Our results also show that these WCET reductions only implied small overhead during WCET analysis.}
}

@misc{MFP+07,
Author = {Peter Marwedel, Heiko Falk, Sascha Plazar, Robert Pyka and Lars Wehmeyer},
Title = {Automatic mapping to tightly-coupled memories and cache locking.},
Year = {(2007).},
Month = {November},
Note = {hfalk, ESD, WCC},
Series = {20071126-hipeac-industrialworkshop-marwedel-falk.pdf},
Address = {Cambridge / UK},
Howpublished = {07-35 MFP+07 HiPEAC},
Type = {Invited Talk at the 4th HiPEAC Industrial Workshop on Compilers and Architectures,}
}

@inproceedings{PFV+07,
Author = {Robert Pyka, Christoph Fa&szlig;bach, Manish Verma, Heiko Falk and Peter Marwedel},
Title = {Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications.},
Year = {(2007).},
Pages = {41-50},
Month = {April},
Note = {hfalk, ESD},
Series = {20070420-scopes-pyka-fassbach.pdf},
Address = {Nice / France},
Isbn = {10.1145/1269843.1269850},
Howpublished = {07-85 PFV+07 SCOPES},
Booktitle = {<em>In Proceedings ot the 10th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Abstract = {Various scratchpad allocation strategies have been developed in the past. Most of them target the reduction of energy consumption. These approaches share the necessity of having direct access to the scratchpad memory. In earlier embedded systems this was always true, but with the increasing complexity of tasks systems have to perform, an additional operating system layer between the hardware and the application is becoming mandatory. This paper presents an approach to integrate a scratchpad memory manager into the operating system. The goal is to minimize energy consumption. In contrast to previous work, compile time knowledge about the application's behavior is taken into account. A set of fast heuristic allocation methods is proposed in this paper. An in-depth study and comparison of achieved energy savings and cycle reductions was performed. The results show that even in the highly dynamic environment of an operating system equipped embedded system, up to 83% energy consumption reduction can be achieved.}
}

@inproceedings{WFG+:2007,
Author = {Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler},
Title = {SWORD: A SAT like prover using word level information.},
Year = {(2007).},
Pages = {88-93},
Note = {gfey, CE},
Howpublished = {07-999 WFG+:2007 VLSISOC},
Booktitle = {<em>IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC)</em>}
}

@article{WFD:2007b,
Author = {Robert Wille and Goerschwin Fey and Rolf Drechsler},
Title = {Building Free Binary Decision Diagrams Using SAT Solvers.},
Journal = {<em>Facta Universitatis</em>.},
Year = {(2007).},
Pages = {381-394},
Note = {gfey, CE},
Howpublished = {07-999 WFD:2007b {FACTA UNIVERSITATIS}}
}

@inproceedings{WFD:2007,
Author = {Robert Wille and Goerschwin Fey and Rolf Drechsler},
Title = {Building Free Binary Decision Diagrams Using SAT Solvers.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 WFD:2007 IWARECD},
Booktitle = {<em>Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design</em>}
}

@article{DFK:2007,
Author = {Rolf Drechsler and Goerschwin Fey and Sebastian Kinder},
Title = {An Integrated Approach for Combining BDDs and SAT Provers.},
Journal = {<em>Facta Universitatis</em>.},
Year = {(2007).},
Pages = {415-436},
Note = {gfey, CE},
Howpublished = {07-999 DFK:2007 {FACTA UNIVERSITATIS}}
}

@inproceedings{KFD:2007,
Author = {Sebastian Kinder and Goerschwin Fey and Rolf Drechsler},
Title = {Estimating the Quality of AND-EXOR Optimization Results.},
Year = {(2007).},
Note = {gfey, CE},
Howpublished = {07-999 KFD:2007 IWARECD},
Booktitle = {<em>Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design</em>}
}

@inproceedings{STF+:2007,
Author = {Stephan Eggersglüß and Daniel Tille and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel},
Title = {Experimental Studies on SAT-based ATPG for Gate Delay Faults.},
Year = {(2007).},
Pages = {6 (6 pages)},
Note = {gfey, CE},
Howpublished = {07-999 STF+:2007 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@inproceedings{EFD:2007,
Author = {Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler},
Title = {SAT-based ATPG for Path Delay Faults in Sequential Circuits.},
Year = {(2007).},
Pages = {3671-3674},
Note = {gfey, CE},
Howpublished = {07-999 EFD:2007 ISCAS},
Booktitle = {<em>IEEE Int'l Symposium on Circuits and Systems (ISCAS)</em>}
}

@inproceedings{EFD+:2007,
Author = {Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel},
Title = {Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.},
Year = {(2007).},
Pages = {181-187},
Note = {gfey, CE},
Howpublished = {07-999 EFD+:2007 MEMOCODE},
Booktitle = {<em>ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE)</em>}
}

@inproceedings{RuVo06,
Author = {Andreas Ruttor and Markus Volkmer},
Title = {Theorie und Anwendungen von Tree Parity Machines f&uuml;r die Kryptographie.},
Year = {(2006).},
Pages = {20-22},
Month = {July},
Note = {AEG},
Address = {Mannheim / Germany},
Howpublished = {06-55 RuVo06 KRYPTO},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (Kryptowochenende 2006)</em>}
}

@phdthesis{Fey:2006,
Author = {Goerschwin Fey},
Title = {Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques.},
Year = {(2006).},
Note = {gfey, CE},
Howpublished = {06-999 Fey:2006},
Type = {Ph.D. Thesis.}
}

@inproceedings{FGD:2006,
Author = {Goerschwin Fey and Daniel Große and Rolf Drechsler},
Title = {Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks.},
Year = {(2006).},
Pages = {1225-1226},
Note = {gfey, CE},
Howpublished = {06-999 FGD:2006 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{FSD:2006,
Author = {Goerschwin Fey and Junhao Shi and Rolf Drechsler},
Title = {Efficiency of multiple-valued encoding in SAT-based ATPG.},
Year = {(2006).},
Pages = {25 (6 pages)},
Note = {gfey, CE},
Howpublished = {06-999 FSD:2006 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@inproceedings{FSD:2006b,
Author = {Goerschwin Fey and Junhao Shi and Rolf Drechsler},
Title = {Efficiency of multiple-valued encoding in SAT-based ATPG.},
Year = {(2006).},
Pages = {107-108},
Note = {gfey, CE},
Howpublished = {06-999 FSD:2006b TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{FD:2006,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {SAT-based Calculation of Source Code Coverage for BMC.},
Year = {(2006).},
Pages = {163-170},
Note = {gfey, CE},
Howpublished = {06-999 FD:2006 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@article{FD:2006b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Minimizing the Number of Paths in BDDs - Theory and Algorithm.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2006).},
Pages = {4-11},
Note = {gfey, CE},
Howpublished = {06-999 FD:2006b TCAD}
}

@inproceedings{FSVD:2006,
Author = {Goerschwin Fey and Sean Safarpour and Andreas Veneris and Rolf Drechsler},
Title = {On the Relation Between Simulation-based and SAT-based Diagnosis.},
Year = {(2006).},
Pages = {1139-1144},
Note = {gfey, CE},
Howpublished = {06-999 FSVD:2006 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{FWD:2006,
Author = {Goerschwin Fey and Tim Warode and Rolf Drechsler},
Title = {Using Structural Learning Techniques in SAT-based ATPG.},
Year = {(2006).},
Pages = {63-69},
Note = {gfey, CE},
Howpublished = {06-999 FWD:2006 IWBP},
Booktitle = {<em>Int'l Workshop on Boolean Problems (IWSBP)</em>}
}

@inproceedings{FaSc06b,
Author = {Heiko Falk and Martin Schwarzer},
Title = {Loop Nest Splitting for WCET-Optimization and Predictability Improvement.},
Year = {(2006).},
Pages = {115-120},
Month = {October},
Note = {hfalk, ESD, WCC},
Series = {20061027-estimedia-falk-schwarzer.pdf},
Address = {Seoul / South Korea},
Isbn = {10.1109/ESTMED.2006.321283},
Howpublished = {06-25 FaSc06b ESTIMedia},
Booktitle = {<em>In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)</em>},
Abstract = {This paper presents the effect of the loop nest splitting source code optimization on worst-case execution time (WCET). Loop nest splitting minimizes the number of executed if-statements in loop nests of multimedia applications. It identifies iterations where all if-statements are satisfied and splits the loop nest such that if-statements are not executed at all for large parts of the loop nest's iteration space.<br /> Especially loops and if-statements are an inherent source of unpredictability and loss of precision for WCET analysis. This is caused by the difficulty to obtain safe and tight worst-case estimates of an application's high-level control flow. In addition, assembly-level control flow redirections reduce predictability even more due to complex processor pipelines and branch prediction units.<br /> Loop nest splitting bases on precise mathematical models combined with genetic algorithms. On the one hand, these techniques achieve a significantly more homogeneous control flow structure. On the other hand, the precision of our analyses enables to generate very accurate high-level flow facts for loops and if-statements. The application of our implemented algorithms to three real-life benchmarks leads to average speed-ups by 25.0% - 30.1%, while WCET is reduced by 34.0% - 36.3%.}
}

@inproceedings{FaSc06a,
Author = {Heiko Falk and Martin Schwarzer},
Title = {Loop Nest Splitting for WCET-Optimization and Predictability Improvement.},
Year = {(2006).},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20060704-wcet-falk-schwarzer.pdf},
Address = {Dresden / Germany},
Isbn = {10.4230/OASIcs.WCET.2006.674},
Howpublished = {06-50 FaSc06a WCET},
Booktitle = {<em>In Proceedings of the 6th International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed if-statements in loop nests of embedded multimedia applications. It identifies iterations of a loop nest where all if-statements are satisfied and splits the loop nest such that if-statements are not executed at all for large parts of the loop nest's iteration space.<br /> Especially loops and if-statements of high-level languages are an inherent source of unpredictability and loss of precision for WCET analysis. This is caused by the fact that it is difficult to obtain safe and tight worst-case estimates of an application's flow of control through these high-level constructs. In addition, the corresponding control flow redirections expressed at the assembly level reduce predictability even more due to the complex pipeline and branch prediction behavior of modern embedded processors.<br /> The analysis techniques for loop nest splitting are based on precise mathematical models combined with genetic algorithms. On the one hand, these techniques achieve a significantly more homogeneous structure of the control flow. On the other hand, the precision of our analyses leads to the generation of very accurate high-level flow facts for loops and if-statements. The application of our implemented algorithms to three real-life multimedia benchmarks leads to average speed-ups by 25.0% - 30.1%, while WCET is reduced between 34.0% and 36.3%.}
}

@inproceedings{FWS06,
Author = {Heiko Falk, Jens Wagner and Andr&eacute; Schaefer},
Title = {Use of a Bit-true Data Flow Analysis for Processor-Specific Source Code Optimization.},
Year = {(2006).},
Pages = {133-138},
Month = {October},
Note = {hfalk, ESD},
Series = {20061027-estimedia-falk-wagner.pdf},
Address = {Seoul / South Korea},
Isbn = {10.1109/ESTMED.2006.321286},
Howpublished = {06-15 FWS06 ESTIMedia},
Booktitle = {<em>In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)</em>},
Abstract = {Nowadays, key characteristics of a processor's instruction set are only exploited in high-level languages by using inline assembly or compiler intrinsics. Inserting intrinsics into the source code is up to the programmer, since only few automatic approaches exist. Additionally, these approaches base on simple code pattern matching strategies.<br /> This paper presents techniques for processor-specific code analysis and optimization at the source-level. It is shown how a bit-true data flow analysis is made applicable for source code analysis for the TI C6x DSPs for the very first time. Based on this bit-true analysis, fully automated optimizations superior to conventional pattern matching techniques are presented which optimize saturated arithmetic, reduce bitwidths of variables and exploit SIMD data processing within source codes. The application of our implemented algorithms to complex real-life codes leads to speed-ups between 33% - 48% for the optimization of saturated arithmetic, and up to 16% after SIMD optimization.}
}

@inproceedings{FLT06b,
Author = {Heiko Falk, Paul Lokuciejewski and Henrik Theiling},
Title = {Design of a WCET-Aware C Compiler.},
Year = {(2006).},
Pages = {121-126},
Month = {October},
Note = {hfalk, ESD, WCC},
Series = {20061027-estimedia-falk-lokuciejewski.pdf},
Address = {Seoul / South Korea},
Isbn = {10.1109/ESTMED.2006.321284},
Howpublished = {06-20 FLT06b ESTIMedia},
Booktitle = {<em>In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)</em>},
Abstract = {This paper presents techniques to integrate worst-case execution time (WCET) data into a compiler. Currently, a tight integration of WCET into compilers is strongly desired, but only some ad-hoc approaches were reported currently. Previous work mainly used self-written WCET estimators with limited functionality and preciseness during compilation. A very tight integration of a high quality WCET analyzer into a compiler was not yet achieved. This work is the first to present such a tight coupling between a compiler and the WCET analyzer aiT. This is done by automatically translating the assembly-like contents of the compiler's low-level format (LLIR) to aiT’s exchange format CRL2. Additionally, the results produced by aiT are automatically collected and re-imported into the compiler infrastructure. The work described in this paper is smoothly integrated into a C compiler for the Infineon TriCore processor. It opens up new possibilities for the design of WCET-aware optimizations in the future.<br /> The concepts for extending the compiler structure are kept very general so that they are not limited to WCET information. Rather, it is possible to use our concepts also for multi-objective optimization of e. g. best-case execution time (BCET) or energy dissipation.}
}

@inproceedings{FLT06a,
Author = {Heiko Falk, Paul Lokuciejewski and Henrik Theiling},
Title = {Design of a WCET-Aware C Compiler.},
Year = {(2006).},
Month = {July},
Note = {hfalk, ESD, WCC},
Series = {20060704-wcet-falk-lokuciejewski.pdf},
Address = {Dresden / Germany},
Isbn = {10.4230/OASIcs.WCET.2006.673},
Howpublished = {06-45 FLT06a WCET},
Booktitle = {<em>In Proceedings of the 6th International Workshop on Worst-Case Execution Time Analysis (WCET)</em>},
Abstract = {This paper presents techniques to tightly integrate worst-case execution time (WCET) information into a compiler framework. Currently, a tight integration of WCET information into the compilation process is strongly desired, but only some ad-hoc approaches have been reported currently. Previous publications mainly used self-written WCET estimators with very limited functionality and preciseness during compilation. A very tight integration of a high quality industry-relevant WCET analyzer into a compiler was not yet achieved up to now. This work is the first to present techniques capable of achieving such a tight coupling between a compiler and the WCET analyzer aiT. This is done by automatically translating the assembly-like contents of the compiler's low-level intermediate representation (LLIR) to aiT’s exchange format CRL2. Additionally, the results produced by the WCET analyzer are automatically collected and re-imported into the compiler infrastructure. The work described in this paper is smoothly integrated into a C compiler environment for the Infineon TriCore processor. It opens up new possibilities for the design of WCET-aware optimizations in the future.<br /> The concepts for extending the compiler infrastructure are kept very general so that they are not limited to WCET information. Rather, it is possible to use our structures also for multi-objective optimization of e. g. best-case execution time (BCET) or energy dissipation.}
}

@techreport{MGIZ06,
Author = {Israel Marck Martinez-Perez, Zhang Gong, Zoya Ignatova and Karl-Heinz Zimmermann},
Title = {Solving the Maximum Clique Problem via DNA Hairpin Formation.},
Year = {(2006).},
Number = {(06.3),},
Month = {December},
Note = {khzimmermann, AEG},
Series = {200612report-2006-06.3-martinez.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.254},
Howpublished = {06-10 MGIZ06 Hamburg},
Type = {Technical Report},
School = {Hamburg University of Technology},
Institution = {Computer Engineering Department}
}

@techreport{MIZ06b,
Author = {Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann},
Title = {An Autonomous DNA Model for Stochastic Finite State Automata.},
Year = {(2006).},
Number = {(06.2),},
Month = {May},
Note = {khzimmermann, AEG},
Series = {200605report-2006-06.2-martinez.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.241},
Howpublished = {06-65 MIZ06b Hamburg},
Type = {Technical Report},
School = {Hamburg University of Technology},
Institution = {Computer Engineering Department}
}

@techreport{MIZ06a,
Author = {Israel Marck Martinez-Perez, Zoya Ignatova and Karl-Heinz Zimmermann},
Title = {An Autonomous DNA Model for Finite State Automata.},
Year = {(2006).},
Number = {(06.1),},
Month = {May},
Note = {khzimmermann, AEG},
Series = {200605report-2006-06.1-martinez.pdf},
Address = {Hamburg / Germany},
Isbn = {10.15480/882.240},
Howpublished = {06-70 MIZ06a Hamburg},
Type = {Technical Report},
School = {Hamburg University of Technology},
Institution = {Computer Engineering Department}
}

@inproceedings{Tyss06,
Author = {Karl Tyss},
Title = {Generatoren f&uuml;r echte Zufallszahlen auf FPGAs f&uuml;r eingebettete Systeme.},
Year = {(2006).},
Pages = {4},
Month = {September},
Note = {AEG},
Address = {Kassel / Germany},
Howpublished = {06-30 Tyss06 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (5. Krypto-Tag)</em>}
}

@book{Zimm06,
Author = {Karl-Heinz Zimmermann},
Title = {Diskrete Mathematik.},
Year = {(2006).},
Month = {August},
Note = {khzimmermann, AEG},
Publisher = {Books on Demand:},
Howpublished = {06-40 Zimm06 BoD}
}

@inproceedings{Volk06,
Author = {Markus Volkmer},
Title = {On proving Completeness, Soundness and Security of Authenticated Tree Parity Machine Key Exchange.},
Year = {(2006).},
Pages = {5},
Month = {May},
Note = {AEG},
Address = {Bochum / Germany},
Howpublished = {06-80 Volk06 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (4. Krypto-Tag)</em>}
}

@misc{Volk06a,
Author = {Markus Volkmer},
Title = {Entity Authentication and Authenticated Key Exchange with Tree Parity Machines.},
Year = {(2006).},
Volume = {<strong>112</strong>.},
Month = {March},
Note = {AEG},
Publisher = {IACR:},
Series = {200603-report-iacr-volkmer.pdf},
Howpublished = {06-90 Volk06a IACR},
Type = {IACR Cryptology ePrint Archive},
Abstract = {This paper provides the first analytical and practical treatment of entity authentication and authenticated key exchange in the framework of Tree Parity Machines (TPMs). The interaction of TPMs has been discussed as an alternative concept for secure symmetric key exchange. Several attacks have been proposed on the non-authenticated principle. Adding and some extra entity authentication method is straightforward but outside the concept using TPMs. A simple and consequent implicit entity authentication from within the key exchange concept as an extension to the key exchange protocol is suggested. A proof for the soundness of the proposed entity authentication is given. Furthermore, next to averting a Man-In-The-Middle attack, the currently known attacks on the non-authenticated symmetric key exchange principle using TPMs can provably be averted for the authenticated variant.}
}

@inproceedings{VoWa06,
Author = {Markus Volkmer and Sebastian Wallner},
Title = {Ein IP-Core Design f&uuml;r Schl&uuml;sselaustausch, Stromchiffre und Identifikation auf ressourcenbeschr&auml;nkten Ger&auml;ten.},
Year = {(2006).},
Pages = {294-297},
Month = {February},
Note = {AEG},
Series = {20060220-sicherheit-volkmer.pdf},
Address = {Magdeburg / Germany},
Howpublished = {06-95 VoWa06 SICHERHEIT},
Booktitle = {<em>In Proceedings of Sicherheit - Schutz und Zuverl&auml;ssigkeit (SICHERHEIT 2006)</em>},
Abstract = {Das Design und die Implementierung f&uuml;r einen sogenannten Lightweight IP-Core f&uuml;r symmetrischen Schl&uuml;sselaustausch, Stromverschl&uuml;sselung und Identifikation (Entity Authentication) werden vorgestellt. Diese dedizierte Hardware-L&ouml;sung bezieht seine drei kryptographischen Funktionen aus einem einzigen adaptiven Interaktionsprotokoll. Sie beansprucht extrem wenig Logik-Fl&auml;che und eignet sich besonders, um die Sicherheit der Kommunikation zwischen ressourcen-beschr&auml;nkten Ger&auml;ten oder zwischen Komponenten (ICs) auf Board-Ebene zu erh&ouml;hen. Der IP-Core beansprucht eine Logik-Fl&auml;che von ca. 0.1 mm<sup>2</sup> bei einem Sechs-Lagen UMC 0.18-Prozess.}
}

@misc{MaFa06,
Author = {Peter Marwedel and Heiko Falk},
Title = {Memory- and timing-aware compilation.},
Year = {(2006).},
Month = {June},
Note = {hfalk, ESD},
Address = {D&uuml;sseldorf / Germany},
Howpublished = {06-60 MaFa06 Nokia},
Type = {Invited Talk at the Nokia Workshop on Compilation for Embedded Systems - State of the Art and Research Issues,}
}

@incollection{DF:2006,
Author = {Rolf Drechsler and Goerschwin Fey},
Title = {Automatic Test Pattern Generation.},
Year = {(2006).},
Pages = {30-55},
Note = {gfey, CE},
Howpublished = {06-999 DF:2006 {SCHOOL ON FORMAL METHODS FOR HARDWARE VERIFICATION}},
Booktitle = {<em>School on Formal Methods for Hardware Verification</em>}
}

@inproceedings{DFK:2006,
Author = {Rolf Drechsler and Goerschwin Fey and Sebastian Kinder},
Title = {An Integrated Approach for Combining BDD and SAT Provers.},
Year = {(2006).},
Pages = {237-242},
Note = {gfey, CE},
Howpublished = {06-999 DFK:2006 VLSIDC},
Booktitle = {<em>VLSI Design Conference</em>}
}

@inproceedings{MVW06,
Author = {Sascha M&uuml;hlbach, Markus Volkmer and Sebastian Wallner},
Title = {Encrypted and Authenticated Communication via Tree-Parity Machines in AMBA Bus Systems.},
Year = {(2006).},
Pages = {10},
Month = {May},
Note = {AEG},
Address = {Bochum / Germany},
Howpublished = {06-75 MVW06 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (4. Krypto-Tag)</em>}
}

@inproceedings{SFBD:2006,
Author = {Stefan Staber and Goerschwin Fey and Roderick Bloem and Rolf Drechsler},
Title = {Automatic Fault Localization for Property Checking.},
Year = {(2006).},
Pages = {50-64},
Note = {gfey, CE},
Howpublished = {06-999 SFBD:2006 HVC},
Booktitle = {<em>IBM Haifa Verification Conference (HVC)</em>}
}

@article{BFD:2005,
Author = {Andreas Breiter and Goerschwin Fey and Rolf Drechsler},
Title = {Project-Based Learning in Student Teams in Computer Science Education.},
Journal = {<em>Facta Universitatis</em>.},
Year = {(2005).},
Pages = {165-180},
Note = {gfey, CE},
Howpublished = {05-999 BFD:2005 {FACTA UNIVERSITATIS}}
}

@inproceedings{Saba05,
Author = {Bj&ouml;rn Saballus},
Title = {Secure Group Communication in WLAN Ad-Hoc Networks with Tree Parity Machines.},
Year = {(2005).},
Pages = {12},
Month = {March},
Note = {AEG},
Address = {Ulm / Germany},
Howpublished = {05-80 Saba05 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (2. Krypto-Tag)</em>}
}

@inproceedings{FD:2005,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Efficient Hierarchical System Debugging for Property Checking.},
Year = {(2005).},
Pages = {41-46},
Note = {gfey, CE},
Howpublished = {05-999 FD:2005 DDECS_WS},
Booktitle = {<em>IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS)</em>}
}

@book{FD:2005b,
Author = {Goerschwin Fey and Rolf Drechsler (editors)},
Title = {FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC.},
Year = {(2005).},
Note = {gfey, CE},
Howpublished = {05-999 FD:2005b}
}

@inproceedings{Falk05,
Author = {Heiko Falk},
Title = {Control Flow driven Code Hoisting at the Source Code Level.},
Year = {(2005).},
Month = {March},
Note = {hfalk, ESD},
Series = {20050320-odes-falk.pdf},
Address = {San Jose / United States},
Howpublished = {05-65 Falk05 ODES},
Booktitle = {<em>In Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES)</em>},
Abstract = {This paper presents a novel source code optimization technique called advanced code hoisting. It aims at moving portions of code from inner loops to outer ones. In contrast to existing code motion techniques, this is done under consideration of control flow aspects. Depending on the conditions of if-statements, moving an expression can lead to an increased number of executions of this expression. This paper contains formal descriptions of the polyhedral models used for control flow analysis so as to suppress a code motion in such a situation. Due to the inherent portability of source code transformations, a very detailed benchmarking using 8 different processors was performed. The application of our implemented techniques to real-life multimedia benchmarks leads to average speed-ups of 25.5% - 52% and energy savings of 33.4% - 74.5%. Furthermore, advanced code hoisting leads to improved pipeline and cache behavior and smaller code sizes.}
}

@article{MGIZ05,
Author = {Israel Marck Martinez-Perez, Zhang Gong, Zoya Ignatova and Karl-Heinz Zimmermann},
Title = {Biomolecular autonomous solution of the Hamiltonian path problem via hairpin formation.},
Journal = {<em>International Journal of Bioinformatics Research and Applications (IJBRA)</em>.},
Year = {(2005).},
Volume = {<strong>1</strong>.},
Number = {(4),},
Pages = {389-398},
Note = {khzimmermann, AEG},
Publisher = {Inderscience:},
Isbn = {10.1504/IJBRA.2005.008442},
Howpublished = {05-95 MGIZ05 IJBRA},
Abstract = {The Hamiltonian path problem is one of the famous hard combinatorial problems. We provide the first molecular-scale autonomous solution of the decision Hamiltonian path problem. It is based on the formation of secondary structures of DNA molecules.}
}

@inproceedings{SFD:2005,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler},
Title = {Bridging Fault Testability of BDD Circuits.},
Year = {(2005).},
Pages = {188-191},
Note = {gfey, CE},
Howpublished = {05-999 SFD:2005 ASPDAC},
Booktitle = {<em>ASP Design Automation Conference (ASPDAC)</em>}
}

@inproceedings{SFD+:2005,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke},
Title = {PASSAT: Efficient SAT-based Test Pattern Generation.},
Year = {(2005).},
Pages = {212-217},
Note = {gfey, CE},
Howpublished = {05-999 SFD+:2005 ISVLSI},
Booktitle = {<em>IEEE Annual Symposium on VLSI (ISVLSI)</em>}
}

@inproceedings{SFD+:2005b,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke},
Title = {Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits.},
Year = {(2005).},
Note = {gfey, CE},
Howpublished = {05-999 SFD+:2005b ASICON},
Booktitle = {<em>IEEE Int'l Conference on ASIC (ASICON)</em>}
}

@inproceedings{SFD+:2005c,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke},
Title = {PASSAT: Efficient SAT-based Test Pattern Generation.},
Year = {(2005).},
Pages = {166-173},
Note = {gfey, CE},
Howpublished = {05-999 SFD+:2005c DDECS_WS},
Booktitle = {<em>IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS)</em>}
}

@article{Zimm05,
Author = {Karl-Heinz Zimmermann},
Title = {Solving constrained combinatorial optimization problems via importance sampling in the grand canonical ensemble.},
Journal = {<em>Computer Physics Communications</em>.},
Year = {(2005).},
Volume = {<strong>165</strong>.},
Number = {(3),},
Pages = {243-259},
Month = {February},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/j.cpc.2004.10.003},
Howpublished = {05-90 Zimm05 CPC},
Abstract = {Combinatorial optimization problems are usually NP-hard. These problems are generally tackled by heuristic or branch-and-bound methods. The aim of this paper is to tackle constrained combinatorial optimization problems by importance Monte Carlo sampling. For this, we show that every constrained combinatorial optimization problem can be represented by a thermodynamical system in a suitable grand canonical ensemble given by the quantities of temperature, volume, and chemical potential. In order to find optimum solutions of the optimization problem, the grand canonical Monte Carlo method can be applied to the corresponding thermodynamical system. This method will amount to importance sampling, i.e. good feasible solutions of the optimization problem will be preferably sampled, provided that the intensive quantities of temperature and chemical potential are appropriately chosen. Our approach extends the standard importance sampling approach in the canonical ensemble to tackle unconstrained combinatorial optimization problems. The knapsack problem is considered as a prototype example.}
}

@article{ElZi05,
Author = {Kolja Elssel and Karl-Heinz Zimmermann},
Title = {Two New Nonlinear Binary Codes.},
Journal = {<em>IEEE Transactions on Information Theory</em>.},
Year = {(2005).},
Volume = {<strong>51</strong>.},
Number = {(3),},
Pages = {1189-1190},
Month = {March},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1109/TIT.2004.842767},
Howpublished = {05-70 ElZi05 TIT},
Abstract = {We present two new binary codes: a (25,384,9) code and a (49,393216,13) code. These codes are better than the currently known binary codes with the same length and minimum distance.}
}

@inproceedings{VPW+05,
Author = {Manish Verma, Klaus Petzold, Lars Wehmeyer, Heiko Falk and Peter Marwedel},
Title = {Scratchpad Sharing Strategies for Multiprocess Embedded Systems: A First Approach.},
Year = {(2005).},
Pages = {115-120},
Month = {September},
Note = {hfalk, ESD},
Series = {20050923-estimedia-verma-petzold.pdf},
Address = {Jersey City / United States},
Isbn = {10.1109/ESTMED.2005.1518087},
Howpublished = {05-35 VPW+05 ESTIMedia},
Booktitle = {<em>In Proceedings of the 3rd IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)</em>},
Abstract = {Portable embedded systems require diligence in managing their energy consumption. Thus, power efficient processors coupled with onchip memories (e.g. caches, scratchpads) are the base of today’s portable devices. Scratchpads are more energy efficient than caches but require software support for their utilization. Portable devices' applications consist of multiple processes for different tasks. However, all the previous scratchpad allocation approaches only consider single process applications. In this paper, we propose a set of optimal strategies to reduce the energy consumption of applications by sharing the scratchpad among multiple processes. The strategies assign both code and data elements to the scratchpad and result in average total energy reductions of 9% - 20% against a published single process approach. Furthermore, the strategies generate Pareto-optimal curves for the applications allowing design time exploration of energy/scratchpad size tradeoffs.}
}

@inproceedings{VoGr05,
Author = {Markus Volkmer and Florian Grewe},
Title = {Runners, Starting Lines and Mutual Distances: On the Security of Tree Parity Machine Key Exchange.},
Year = {(2005).},
Pages = {5},
Month = {September},
Note = {AEG},
Address = {Darmstadt / Germany},
Howpublished = {05-40 VoGr05 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (3. Krypto-Tag)</em>}
}

@inproceedings{VoWa05d,
Author = {Markus Volkmer and Sebastian Wallner},
Title = {A Key Establishment IP-Core for Ubiquitous Computing.},
Year = {(2005).},
Pages = {241-245},
Month = {August},
Note = {AEG},
Address = {Copenhagen / Denmark},
Isbn = {10.1109/DEXA.2005.18},
Howpublished = {05-45 VoWa05d Krypto},
Booktitle = {<em>In Proceedings of 16th International Workshop on Database and Expert Systems Applications</em>},
Abstract = {A most critical and complex issue with regard to constrained devices in the ubiquitous and pervasive computing setting is secure key exchange. The restrictions motivate the investigation and discussion of alternative solutions. We suggest a low hardware-complexity solution for authenticated symmetric key exchange, using a tree parity machine rekeying architecture. An authenticated key exchange is formulated from within the tree parity machine interaction concept and requires only few transmissions. It averts a man-in-the-middle attack and the currently known attacks on the non-numbertheoretic on principle. A key exchange can be performed within a few milliseconds, given typical limited bandwidth wireless communication channels. Characteristics of a standard-cell ASIC design realization as IP-core in 0.18mu-CMOS technology are evaluated.}
}

@misc{VoWa05c,
Author = {Markus Volkmer and Sebastian Wallner},
Title = {Tree Parity Machine Rekeying Architectures for Embedded Security.},
Year = {(2005).},
Volume = {<strong>235</strong>.},
Month = {July},
Note = {AEG},
Publisher = {IACR:},
Series = {200507-report-iacr-volkmer.pdf},
Howpublished = {05-50 VoWa05c IACR},
Type = {IACR Cryptology ePrint Archive},
Abstract = {Nonclassical cryptographic technologies are considered in science and industry to provide alternative security solutions. They are motivated by the strong restrictions as they are often present in embedded security scenarios and in applications of pervasive computing. We investigate a low hardware-complexity cryptosystem for lightweight symmetric key exchange, based on two new Tree Parity Machine Rekeying Architectures (TPMRAs). The speed of a key exchange is basically only limited by the channel capacity. This work significantly improves and extends previously published results on TPMRAs. We evaluate characteristics of standard-cell ASIC design realizations as IP-core in 0.18-micrometer-CMOS technology.}
}

@inproceedings{VoWa05b,
Author = {Markus Volkmer and Sebastian Wallner},
Title = {Lightweight Key Exchange and Stream Cipher based solely on Tree Parity Machines.},
Year = {(2005).},
Month = {July},
Note = {AEG},
Series = {20050714-ecrypt-volkmer.pdf},
Address = {Graz / Austria},
Howpublished = {05-55 VoWa05b ECRYPT},
Booktitle = {<em>In Proceedings of the ECRYPT Workshop on RFID and Lightweight Crypto</em>},
Abstract = {Alternative security solutions are considered in science and industry, motivated by the strong restrictions as they are often present in embedded security scenarios - especially in a RFID setting. We investigate a low hardware-complexity cryptosystem for lightweight symmetric key exchange and stream cipher based on Tree Parity Machines. The speed of a key exchange is basically only limited by the channel capacity as is the stream cipher throughput. This work significantly improves and extends previously published results on TPMRAs. Again, characteristics of standard-cell ASIC design realizations as IP-core in 0.18-micrometer-CMOS technology are evaluated.}
}

@article{VoWa05a,
Author = {Markus Volkmer and Sebastian Wallner},
Title = {Tree parity machine rekeying architectures.},
Journal = {<em>IEEE Transactions on Computers</em>.},
Year = {(2005).},
Volume = {<strong>54</strong>.},
Number = {(4),},
Pages = {421-427},
Month = {April},
Note = {AEG},
Publisher = {IEEE:},
Isbn = {10.1109/TC.2005.70},
Howpublished = {05-60 VoWa05a TC},
Abstract = {The necessity of securing the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e., small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronization of tree parity machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration, we evaluate characteristics of a standard-cell ASIC design realization as IP-core in 0.18μ-technology.}
}

@inproceedings{Behr05,
Author = {Nazita Behroozi},
Title = {Immediate Rekeying by Tree Parity Machines in a WLAN-System.},
Year = {(2005).},
Pages = {10},
Month = {March},
Note = {AEG},
Address = {Ulm / Germany},
Howpublished = {05-85 Behr05 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (2. Krypto-Tag)</em>}
}

@inproceedings{DFGG:2005,
Author = {Rolf Drechsler and Goerschwin Fey and Christian Genz and Daniel Große},
Title = {SyCE: An Integrated Environment for System Design in SystemC.},
Year = {(2005).},
Pages = {258-260},
Note = {gfey, CE},
Howpublished = {05-999 DFGG:2005 RSP_WS},
Booktitle = {<em>IEEE Int'l Workshop on Rapid System Prototyping (RSP)</em>}
}

@book{EFD:2005,
Author = {Rüdiger Ebendt and Goerschwin Fey and Rolf Drechsler},
Title = {Advanced BDD Optimization.},
Year = {(2005).},
Note = {gfey, CE},
Howpublished = {05-999 EFD:2005}
}

@inproceedings{SFVD:2005,
Author = {Sean Safarpour and Goerschwin Fey and Andreas Veneris and Rolf Drechsler},
Title = {Utilizing Don't Care States in SAT-based Bounded Sequential Problems.},
Year = {(2005).},
Pages = {264-269},
Note = {gfey, CE},
Howpublished = {05-999 SFVD:2005 GLS},
Booktitle = {<em>Great Lakes Symp. VLSI (GLS)</em>}
}

@inproceedings{KFD:2005,
Author = {Sebastian Kinder and Goerschwin Fey and Rolf Drechsler},
Title = {Controlling the Memory During Manipulation of Word-Level Decision Diagrams.},
Year = {(2005).},
Pages = {250-255},
Note = {gfey, CE},
Howpublished = {05-999 KFD:2005 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@inproceedings{Scha04,
Author = {Andr&eacute; Schaumburg},
Title = {Authentication within Tree Parity Machine Rekeying.},
Year = {(2004).},
Pages = {13},
Month = {December},
Note = {AEG},
Address = {Mannheim / Germany},
Howpublished = {04-70 Scha04 Krypto},
Booktitle = {<em>In Proceedings of Workshop &uuml;ber Kryptographie (1. Krypto-Tag)</em>}
}

@inproceedings{FGC+:2004,
Author = {Goerschwin Fey and Daniel Große and Tim Cassens and Christian Genz and Tim Warode and Rolf Drechsler},
Title = {ParSyC: An Efficient SystemC Parser.},
Year = {(2004).},
Pages = {148-154},
Note = {gfey, CE},
Howpublished = {04-999 FGC+:2004 SASIMI},
Booktitle = {<em>Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)</em>}
}

@inproceedings{FSD:2004,
Author = {Goerschwin Fey and Junhao Shi and Rolf Drechsler},
Title = {BDD Circuit Optimization for Path Delay Fault Testability.},
Year = {(2004).},
Pages = {162-172},
Note = {gfey, CE},
Howpublished = {04-999 FSD:2004 DSD_EUROMICRO},
Booktitle = {<em>EUROMICRO Symposium on Digital System Design (DSD)</em>}
}

@inproceedings{FD:2004,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Improving Simulation-Based Verification by Means of Formal Methods.},
Year = {(2004).},
Pages = {640-643},
Note = {gfey, CE},
Howpublished = {04-999 FD:2004 ASPDAC},
Booktitle = {<em>ASP Design Automation Conference (ASPDAC)</em>}
}

@inproceedings{FD:2004b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Visualization of Diagnosis Results for Design Debugging.},
Year = {(2004).},
Pages = {1-2},
Note = {gfey, CE},
Howpublished = {04-999 FD:2004b ULSIWS},
Booktitle = {<em>Internatinal Workshop on Post-Binary ULSI Systems (ULSIWS)</em>}
}

@inproceedings{FDC:2004,
Author = {Goerschwin Fey and Rolf Drechsler and Maciej Ciesielski},
Title = {Algorithms for Taylor Expansion Diagrams.},
Year = {(2004).},
Pages = {235-240},
Note = {gfey, CE},
Howpublished = {04-999 FDC:2004 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@phdthesis{Falk04,
Author = {Heiko Falk},
Title = {Source Code Optimization Techniques for Data Flow Dominated Embedded Software.},
Year = {(2004).},
Month = {June},
Note = {hfalk, ESD},
Series = {20040603-phdthesis-toc-falk.pdf},
Address = {Dortmund / Germany},
Howpublished = {04-90 Falk04 PhD},
Type = {Ph.D. Thesis.},
School = {University of Dortmund},
Institution = {Faculty of Computer Science},
Abstract = {Usually, optimizations are applied by compilers which translate source code into machine code for a specific processor. Recently, transformations taking place before compilation are attracting interest. Such source code optimizations have the following advantages over compiler-integrated approaches:<br /> First, source code optimizations are inherently portable, since the optimized source code can be compiled by any compiler for the considered source language. Second, the correctness of source code transformations is often easier to validate, since faster servers can be used due to the portability, instead of slow evaluation hardware or instruction set simulators. Third, source code optimizations are easy to integrate into existing industrial tool chains. Fourth, source code transformations are easier to understand due to their high abstraction level as compared to machine code optimizations.<br /> The examination of the source codes of embedded multimedia applications in this Ph. D. thesis revealed that such software only uses a small fraction of its execution time to compute audio or video data. Most of the execution time is used to evaluate and execute the complex control flow inside these multimedia algorithms. The source code optimizations proposed in this Ph. D. thesis thus focus on the analysis of the control flow of multimedia applications, and on its improvement. All proposed techniques are jointly able to reduce the execution times of realistic applications on average over nine different processor architectures by 69%. Furthermore, cumulative energy reductions by 83% have been observed.}
}

@inproceedings{FaVe04,
Author = {Heiko Falk and Manish Verma},
Title = {Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization.},
Year = {(2004).},
Pages = {137-151},
Month = {September},
Note = {hfalk, ESD},
Series = {20040903-scopes-falk-verma.pdf},
Address = {Amsterdam / The Netherlands},
Isbn = {10.1007/978-3-540-30113-4_11},
Howpublished = {04-85 FaVe04 SCOPES},
Booktitle = {<em>In Proceedings of the 8th International Workshop on Software & Compilers for Embedded Systems (SCOPES)</em>},
Type = {<strong>Best Paper Candidate</strong>.},
Abstract = {For mobile embedded systems, the energy consumption is a limiting factor because of today's battery capacities. Besides the processor, memory accesses consume a high amount of energy. The use of additional less power hungry memories like caches or scratchpads is thus common. This paper presents a combined approach for energy consumption minimization consisting of two complementary and phase-coupled optimizations, viz. data partitioning and loop nest splitting. In a first step, data partitioning partitions large arrays found in typical embedded software into smaller ones which are placed onto an on-chip scratchpad memory. Although being effective w.r.t. energy dissipation, this optimization adds overhead to the code since the correct part of a partitioned array has to be selected at runtime. Therefore, the control flow is optimized as a second step in our framework. In this phase, loop nests containing if-statements are split using genetic algorithms leading to minimized if-statement executions. However, loop nest splitting leads to an increase in code size and can potentially annul the program layout achieved by the first step. Consequently, the proposed approach iteratively applies these optimizations till a local optimum is found. The proposed framework of combined memory and control flow optimization leads to considerable energy savings for a representative set of typical embedded software routines. Using an accurate energy model for the ARM7 processor, energy savings between 20.3% and 43.3% were measured.}
}

@book{FaMa04,
Author = {Heiko Falk and Peter Marwedel},
Title = {Source Code Optimization Techniques for Data Flow Dominated Embedded Software.},
Year = {(2004).},
Month = {October},
Note = {hfalk, ESD},
Publisher = {Kluwer Academic Publishers:},
Isbn = {10.1007/978-1-4020-2829-8},
Howpublished = {04-75 FaMa04 Kluwer},
Abstract = {The building blocks of today's embedded systems-on-a-chip (SoC) are complex IP components and programmable processor cores. This means that more and more system functionality is implemented in software rather than in custom hardware motivating the need for highly optimized embedded software.<br /> Source Code Optimization Techniques for Data Flow Dominated Embedded Software is the first contribution focusing on the application of optimizations outside a compiler at the source code level. This book covers the following areas: - Several entirely new techniques are presented in combination with efficient algorithms for the most important ones. - Control flow analysis and optimization of data-dominated applications is one of the main contributions of this book since this issue remained open up to now. - Using real-life applications, large improvements in terms of runtimes and energy dissipation were achieved by the techniques presented in this book. Detailed results for a broad range of processors including DSPs, VLIWs and embedded RISC cores are discussed.}
}

@inproceedings{WTSF:2004,
Author = {Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey},
Title = {Cost-efficient Block Verification for a UMTS Up-link Chip-rate Coprocessor.},
Year = {(2004).},
Pages = {162-167},
Note = {gfey, CE},
Howpublished = {04-999 WTSF:2004 DATE},
Booktitle = {<em>Design, Automation and Test in Europe (DATE)</em>}
}

@inproceedings{VoWa04,
Author = {Markus Volkmer and Sebastian Wallner},
Title = {A Low-Cost Solution for Frequent Symmetric Key Exchange in Ad-hoc Networks.},
Year = {(2004).},
Pages = {128-132},
Month = {September},
Note = {AEG},
Series = {20040920-wman-volkmer.pdf},
Address = {Ulm / Germany},
Howpublished = {04-80 VoWa04 WMAN},
Booktitle = {<em>In Proceedings of the Workshop Mobile Ad-hoc Netzwerke (WMAN)</em>},
Abstract = {Next to authentication, secure key exchange is considered the most critical and complex issue regarding ad-hoc network security. We present a low-cost, (i.e. low hardware-complexity) solution for feasible frequent symmetric key exchange in ad-hoc networks, based on a Tree Parity Machine Rekeying Architecture. A key exchange can be performed within a few milliseconds, given practical wireless communication channels and their limited bandwidths. A flexible rekeying functionality enables the full exploitation of the achievable key exchange rates. Characteristics of a standard-cell ASIC design realisation as IP-core in 0.18 micrometer-technology are evaluated.}
}

@inproceedings{DHFD:2004,
Author = {Nicole Drechsler and Mario Hilgemeier and Goerschwin Fey and Rolf Drechsler},
Title = {Disjoint Sum of Product Minimization by Evolutionary Algorithms.},
Year = {(2004).},
Pages = {198-207},
Note = {gfey, CE},
Howpublished = {04-999 DHFD:2004 {APPLICATIONS OF EVOLUTIONARY COMPUTING: EVOWORKSHOPS}},
Booktitle = {<em>Applications of Evolutionary Computing: EvoWorkshops</em>}
}

@inproceedings{FD:2004c,
Author = {Rolf Drechsler and Goerschwin Fey},
Title = {Design Understanding by Automatic Property Generation.},
Year = {(2004).},
Pages = {274-281},
Note = {gfey, CE},
Howpublished = {04-999 FD:2004c SASIMI},
Booktitle = {<em>Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)</em>}
}

@article{DSF:2004,
Author = {Rolf Drechsler and Junhao Shi and Goerschwin Fey},
Title = {Synthesis of Fully Testable Circuits from BDDs.},
Journal = {<em>IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD)</em>.},
Year = {(2004).},
Pages = {440-443},
Note = {gfey, CE},
Howpublished = {04-999 DSF:2004 TCAD}
}

@techreport{APZ04,
Author = {Wolfgang Achtziger, Andreas Popp and Karl-Heinz Zimmermann},
Title = {Optimization and Parallelization of Loop Nests via Linear Vector-Valued Schedules.},
Year = {(2004).},
Number = {(#264),},
Month = {June},
Note = {khzimmermann, AEG},
Address = {Dortmund / Germany},
Howpublished = {04-95 APZ04 Dortmund},
Type = {Technical Report},
School = {University of Dortmund},
Institution = {Faculty of Mathematics},
Abstract = {Automatic transformation of a sequential program into a parallel form has a large practical impact. The most common parallelization methods used are loop-level transformations based on unimodular transformations which largely use linear schedules. In this paper, we provide a method which allows to construct multidimensional schedules for loop nests. For this, we approximate the problem of finding optimal multidimensional schedules for a loop nest by a real-valued problem which can be solved by standard algorithms for optimization problems.}
}

@inproceedings{GFD:2003,
Author = {Daniel Große and Goerschwin Fey and Rolf Drechsler},
Title = {Modeling Multi-Valued Circuits in SystemC.},
Year = {(2003).},
Pages = {281-286},
Note = {gfey, CE},
Howpublished = {03-999 GFD:2003 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@inproceedings{FSD:2003,
Author = {Goerschwin Fey and Junhao Shi and Rolf Drechsler},
Title = {BDD Circuit Optimization for Path Delay Fault-Testability.},
Year = {(2003).},
Note = {gfey, CE},
Howpublished = {03-999 FSD:2003 TUZ},
Booktitle = {<em>GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ)</em>}
}

@inproceedings{FD:2003,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization.},
Year = {(2003).},
Pages = {54-60},
Note = {gfey, CE},
Howpublished = {03-999 FD:2003 SASIMI},
Booktitle = {<em>Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)</em>}
}

@inproceedings{FD:2003b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Finding Good Counter-Examples to Aid Design Verification.},
Year = {(2003).},
Pages = {51-52},
Note = {gfey, CE},
Howpublished = {03-999 FD:2003b MEMOCODE},
Booktitle = {<em>ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE)</em>}
}

@inproceedings{FKD:2003,
Author = {Goerschwin Fey and Sebastian Kinder and Rolf Drechsler},
Title = {Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques.},
Year = {(2003).},
Pages = {361-366},
Note = {gfey, CE},
Howpublished = {03-999 FKD:2003 ISMVL},
Booktitle = {<em>IEEE Int'l Symposium on Multi-Valued Logic (ISMVL)</em>}
}

@misc{Falk03,
Author = {Heiko Falk},
Title = {Source Code Optimization Techniques for Data Flow Dominated Embedded Software.},
Year = {(2003).},
Month = {November},
Note = {hfalk, ESD},
Address = {Dresden / Germany},
Howpublished = {03-70 Falk03 DSP},
Type = {Invited Talk at the DSP Design Workshop,}
}

@inproceedings{FaMa03,
Author = {Heiko Falk and Peter Marwedel},
Title = {Control Flow driven Splitting of Loop Nests at the Source Code Level.},
Year = {(2003).},
Pages = {410-415},
Month = {March},
Note = {hfalk, ESD},
Series = {20030305-date-falk-marwedel.pdf},
Address = {Munich / Germany},
Isbn = {10.1109/DATE.2003.10158},
Howpublished = {03-90 FaMa03 DATE},
Booktitle = {<em>In Proceedings of Design, Automation and Test in Europe (DATE)</em>},
Type = {<strong>Best Paper Candidate</strong>.},
Abstract = {This paper presents a novel source code transformation for control flow optimization called loop nest splitting which minimizes the number of executed if-statements in loop nests of embedded multimedia applications. The goal of the optimization is to reduce runtimes and energy consumption. The analysis techniques are based on precise mathematical models combined with genetic algorithms. Due to the inherent portability of source code transformations, a very detailed benchmarking using 10 different processors can be performed. The application of our implemented algorithms to three real-life multimedia benchmarks leads to average speed-ups by 23.6% - 62.1% and energy savings by 19.6% - 57.7%. Furthermore, our optimization also leads to advantageous pipeline and cache performance.}
}

@inproceedings{FGML03,
Author = {Heiko Falk, C&eacute;dric Ghez, Miguel Miranda and Rainer Leupers},
Title = {High-level Control Flow Transformations for Performance Improvement of Address-Dominated Multimedia Applications.},
Year = {(2003).},
Pages = {338-344},
Month = {April},
Note = {hfalk, ESD},
Series = {20030404-sasimi-falk-ghez.pdf},
Address = {Hiroshima / Japan},
Howpublished = {03-85 FGML03 SASIMI},
Booktitle = {<em>In Proceedings of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)</em>},
Abstract = {This paper describes a set of novel high-level control flow transformations for performance improvement of typical address-dominated multimedia applications. We show that these transformations applied at the source code level can have a very large impact on execution time at the cost of limited overhead in code size for a broad range of instruction set processor families (i. e. CISC, RISC, DSP, VLIW, ...). For a profound evaluation, all transformations are applied to the C-codes of two real-life applications selected from the video and image processing domains. A detailed analysis of the effect of the transformations is done by compiling and executing the transformed programs on seven different programmable processors. The measured runtimes indicate quite significant improvements in all processor families when comparing the performance of the transformed codes to their initial version even when these are compiled using their native optimizing compilers with their most aggressive optimization features enabled. The average gains in execution time range from 40.2% and 87.7% depending on the driver, with an average overhead in code size between 21.1% and 100.9%.}
}

@inbook{FMC03,
Author = {Heiko Falk, Peter Marwedel and Francky Catthoor},
Title = {Control Flow driven Splitting of Loop Nests at the Source Code Level.},
Year = {(2003).},
Pages = {215-229},
Month = {September},
Note = {hfalk, ESD},
Editor = {In A. Jerraya, S. Yoo, D. Verkest and N. Wehn (Eds.)},
Publisher = {Kluwer Academic Publishers:},
Isbn = {10.1007/0-306-48709-8_17},
Howpublished = {03-80 FMC03 Kluwer},
Booktitle = {<em>Embedded Software for SoC</em>},
chapter = {17},
Abstract = {This article presents a novel source code transformation for control flow optimization called loop nest splitting which minimizes the number of executed if-statements in loop nests of embedded multimedia applications. The goal of the optimization is to reduce runtimes and energy consumption. The analysis techniques are based on precise mathematical models combined with genetic algorithms. The application of our implemented algorithms to three real-life multimedia benchmarks using 10 different processors leads to average speed-ups by 23.6% - 62.1% and energy savings by 19.6% - 57.7%. Furthermore, our optimization also leads to advantageous pipeline and cache performance.}
}

@inproceedings{SFD:2003,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler},
Title = {BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.},
Year = {(2003).},
Pages = {290-293},
Note = {gfey, CE},
Howpublished = {03-999 SFD:2003 ATS},
Booktitle = {<em>Asian Test Symposium (ATS)</em>}
}

@inproceedings{SFD:2003a,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler},
Title = {BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.},
Year = {(2003).},
Pages = {109-110},
Note = {gfey, CE},
Howpublished = {03-999 SFD:2003a ETW},
Booktitle = {<em>IEEE European Test Workshop (ETW)</em>}
}

@inproceedings{SFD:2003b,
Author = {Junhao Shi and Goerschwin Fey and Rolf Drechsler},
Title = {Random Pattern Testability of Circuits Derived from BDDs.},
Year = {(2003).},
Pages = {70-78},
Note = {gfey, CE},
Howpublished = {03-999 SFD:2003b WRTLT},
Booktitle = {<em>IEEE Workshop on RTL and High Level Testing (WRTLT)</em>}
}

@article{Zimm03b,
Author = {Karl-Heinz Zimmermann},
Title = {A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(2003).},
Volume = {<strong>35</strong>.},
Number = {(3),},
Pages = {297-309},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1023/B:VLSI.0000003027.47559.1e},
Howpublished = {03-75 Zimm03b JVLSI},
Abstract = {Point mutation of amino acids is a means used by biotechnologists to improve the performance of proteins. To study a point-mutated polypeptide, one requires its global minimum energy conformation. This conformation can be determined by molecular dynamics via Langevin's equations of motion. Molecular dynamics simulations belong to the most difficult problems to parallelize in a scalable manner. We provide a method for defining a special purpose 3D array processor architecture for the molecular dynamics simulation of point-mutated polypeptides. The architecture is derived from a spatial decomposition of a known conformation of the point-mutated polypeptide or the native conformation of the given protein. By using an approximation scheme for the deterministic forces, the interprocessor communication can be kept local. The architecture affords a simple distributed load balancer and is scalable. The computational workload of the array processor architecture to perform molecular dynamics simulations under realistic conditions is addressed. An example architecture is given by point-mutated penicillin amidase.}
}

@book{Zimm03a,
Author = {Karl-Heinz Zimmermann},
Title = {An Introduction to Protein Informatics.},
Year = {(2003).},
Note = {khzimmermann, AEG},
Publisher = {Kluwer Academic Publishers:},
Isbn = {10.1007/978-1-4419-9210-9},
Howpublished = {03-95 Zimm03? Kluwer},
Abstract = {Protein informatics is a newer name for an already existing discipline. It encompasses the techniques used in bioinformatics and molecular modeling that are related to proteins. While bioinformatics is mainly concerned with the collection, organization, and analysis of biological data, molecular modeling is devoted to representation and manipulation of the structure of proteins. <br /> Protein informatics requires substantial prerequisites on computer science, mathematics, and molecular biology. The approach chosen here, allows a direct and rapid grasp on the subject starting from basic knowledge of algorithm design, calculus, linear algebra, and probability theory.<br /> An Introduction to Protein Informatics, a professional monograph will provide the reader a comprehensive introduction to the field of protein informatics. The text emphasizes mathematical and computational methods to tackle the central problems of alignment, phylogenetic reconstruction, and prediction and sampling of protein structure. <br /> An Introduction to Protein Informatics is designed for a professional audience, composed of researchers and practitioners within bioinformatics, molecular modeling, algorithm design, optimization, and pattern recognition. This book is also suitable as a graduate-level text for students in computer science, mathematics, and biomedicine.}
}

@inproceedings{WTSF:2003,
Author = {Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey},
Title = {Cost-efficient Formal Block Verification for ASIC Design.},
Year = {(2003).},
Pages = {184-188},
Note = {gfey, CE},
Howpublished = {03-999 WTSF:2003 MBMV},
Booktitle = {<em>ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</em>}
}

@inproceedings{DSF:2003,
Author = {Rolf Drechsler and Junhao Shi and Goerschwin Fey},
Title = {MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits.},
Year = {(2003).},
Pages = {80-83},
Note = {gfey, CE},
Howpublished = {03-999 DSF:2003 GLS},
Booktitle = {<em>Great Lakes Symp. VLSI (GLS)</em>}
}

@inproceedings{FD:2002b,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Utilizing BDDs for Disjoint SOP Minimization.},
Year = {(2002).},
Pages = {306-309},
Note = {gfey, CE},
Howpublished = {02-999 FD:2002b MWSCAS},
Booktitle = {<em>IEEE Midwest Symposium on Circuits and Systems (MWSCAS)</em>}
}

@inproceedings{FD:2002a,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Minimizing the Number of Paths in BDDs.},
Year = {(2002).},
Pages = {359-364},
Note = {gfey, CE},
Howpublished = {02-999 FD:2002a SBCCI},
Booktitle = {<em>Symposium on Integrated Circuits and Systems Design (SBCCI)</em>}
}

@inproceedings{FD:2002,
Author = {Goerschwin Fey and Rolf Drechsler},
Title = {Minimizing the Number of Paths in BDDs.},
Year = {(2002).},
Note = {gfey, CE},
Howpublished = {02-999 FD:2002 IWBP},
Booktitle = {<em>Int'l Workshop on Boolean Problems (IWSBP)</em>}
}

@techreport{Falk02,
Author = {Heiko Falk},
Title = {Control Flow Optimization by Loop Nest Splitting at the Source Code Level.},
Year = {(2002).},
Number = {(#773),},
Month = {October},
Note = {hfalk, ESD},
Series = {20021018-report-773-falk.pdf},
Address = {Dortmund / Germany},
Howpublished = {02-85 Falk02 Dortmund},
Type = {Technical Report},
School = {University of Dortmund},
Institution = {Faculty of Computer Science},
Abstract = {In recent years, the application of optimization techniques at the level of program source codes has increasingly attracted interest due to the high effectiveness and the inherent retargetability of such approaches. In this report, a novel source code transformation technique for control flow optimization called loop nest splitting is presented. The goal of this optimization is to reduce runtimes and energy consumption by minimizing the number of if-statements executed in loop nests of typical embedded multimedia applications. Complementary to already known optimizations in this area, we explicitly focus on the optimization of loop-variant if-statements. The analysis techniques required for performing loop nest splitting are illustrated in detail. They base on precise mathematic models combined with genetic algorithms. The analysis is done statically at compile time and does not rely on profiling.<br /> For a detailed evaluation of the benefits of loop nest splitting, the effects of our optimization with respect to instruction pipeline and cache behavior, runtimes, energy consumption and code sizes are shown. The application of our implemented tools for loop nest splitting to three real-life multimedia benchmarks leads to average reductions of pipeline stalls between 19.7% and 64.8% and an average decrease of instruction cache misses between 8.9% and 45.3%. Measurements on a variety of different programmable processors show average speed-ups between 23.6% and 62.1% of the benchmarks, whereas reductions of energy dissipation between 19.2% and 57.6% are observed.}
}

@inproceedings{RFM:2002,
Author = {Jörg Ritter and Goerschwin Fey and Paul Molitor},
Title = {SPIHT implemented in a XC4000 device.},
Year = {(2002).},
Pages = {239-242},
Note = {gfey, CE},
Howpublished = {02-999 RFM:2002 MWSCAS},
Booktitle = {<em>IEEE Midwest Symposium on Circuits and Systems (MWSCAS)</em>}
}

@article{Zimm02b,
Author = {Karl-Heinz Zimmermann},
Title = {Efficient DNA sticker algorithms for NP-complete graph problems.},
Journal = {<em>Computer Physics Communications</em>.},
Year = {(2002).},
Volume = {<strong>144</strong>.},
Number = {(3),},
Pages = {297-309},
Month = {April},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/S0010-4655(02)00270-9},
Howpublished = {02-90 Zimm02b CPC},
Abstract = {Adleman's successful solution of a seven-vertex instance of the NP-complete Hamiltonian directed path problem by a DNA algorithm initiated the field of biomolecular computing. We provide DNA algorithms based on the sticker model to compute all k-cliques, independent k-sets, Hamiltonian paths, and Steiner trees with respect to a given edge or vertex set. The algorithms determine not merely the existence of a solution but yield all solutions (if any). For an undirected graph with n vertices and m edges, the running time of the algorithms is linear in n+m. For this, the sticker algorithms make use of small combinatorial input libraries instead of commonly used large libraries. The described algorithms are entirely theoretical in nature. They may become very useful in practice, when further advances in biotechnology lead to an efficient implementation of the sticker model.}
}

@article{Zimm02a,
Author = {Karl-Heinz Zimmermann},
Title = {On applying molecular computation to binary linear codes.},
Journal = {<em>IEEE Transactions on Information Theory</em>.},
Year = {(2002).},
Volume = {<strong>48</strong>.},
Number = {(2),},
Pages = {505-510},
Month = {February},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1109/18.979325},
Howpublished = {02-95 Zimm02a TIT},
Abstract = {Adleman's (1994) successful solution of a seven-vertex instance of the NP-complete Hamiltonian directed path problem by a DNA algorithm initiated the field of biomolecular computing. In this correspondence, we describe DNA algorithms based on the sticker model to perform encoding, minimum-distance computation, and maximum-likelihood (ML) decoding of binary linear codes. We also discuss feasibility and limitations of the sticker algorithms.}
}

@article{PoZi01,
Author = {Andreas Popp and Karl-Heinz Zimmermann},
Title = {On loop transformations of nested loops with affine dependencies.},
Journal = {<em>Computer Physics Communications</em>.},
Year = {(2001).},
Volume = {<strong>139</strong>.},
Number = {(1),},
Pages = {90-103},
Month = {September},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/S0010-4655(01)00232-6},
Howpublished = {01-85 PoZi01 CPC},
Abstract = {Automatic transformation of a sequential program into a parallel form has a large practical impact. In particular, the parallelization of loop nests with uniform dependencies is well understood. The most common parallelization methods used are loop-level transformations based on unimodular transformations, and the most useful unimodular transformations are inner and outer loop parallelization which are built on linear schedules. In this paper, we consider a larger class of loop nests: loop nests with affine dependencies. For affine loop nests, we provide a generalization of both, inner and outer loop parallelization. For this, the dependencies of the extremal points of the index space need to be considered. We sketch an implementation of our parallelization techniques, and outline a method for the synthesis of array processors from affine loop nests.}
}

@mastersthesis{Fey:2001,
Author = {Goerschwin Fey},
Title = {Set Partitioning in Hierarchical Trees: eine FPGA-Implementierung.},
Year = {(2001).},
Note = {gfey, CE},
Howpublished = {01-999 Fey:2001},
Type = {Diploma Thesis}
}

@article{ZiAc01,
Author = {Karl-Heinz Zimmermann and Wolfgang Achtziger},
Title = {Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming.},
Journal = {<em>Computer Physics Communications</em>.},
Year = {(2001).},
Volume = {<strong>139</strong>.},
Number = {(1),},
Pages = {64-89},
Month = {September},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/S0010-4655(01)00231-4},
Howpublished = {01-90 ZiAc01 CPC},
Abstract = {The size of a systolic array synthesized from a uniform recurrence equation, whose computations are mapped by a linear function to the processors, matches the problem size. In practice, however, there exist several limiting factors on the array size. There are two dual schemes available to derive arrays of smaller size from large-size systolic arrays based on the partitioning of the large-size arrays into subarrays. In LSGP, the subarrays are clustered one-to-one into the processors of a small-size array, while in LPGS, the subarrays are serially assigned to a reduced-size array. <br /> In this paper, we propose a common methodology for both LSGP and LPGS based on polyhedral partitionings of large-size k-dimensional systolic arrays which are synthesized from n-dimensional uniform recurrences by linear mappings for allocation and timing. In particular, we address the optimization problem of finding optimal piecewise linear timing functions for small-size arrays. These are mappings composed of linear timing functions for the computations of the subarrays. We study a continuous approximation of this problem by passing from piecewise linear to piecewise quasi-linear timing functions. The resultant problem formulation is then a quadratic programming problem which can be solved by standard algorithms for nonlinear optimization problems.}
}

@article{ZiAc01,
Author = {Karl-Heinz Zimmermann and Wolfgang Achtziger},
Title = {Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming.},
Journal = {<em>Computer Physics Communications</em>.},
Year = {(2001).},
Volume = {<strong>139</strong>.},
Number = {(1),},
Pages = {64-89},
Month = {September},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/S0010-4655(01)00231-4},
Howpublished = {01-90 ZiAc01 CPC},
Abstract = {The size of a systolic array synthesized from a uniform recurrence equation, whose computations are mapped by a linear function to the processors, matches the problem size. In practice, however, there exist several limiting factors on the array size. There are two dual schemes available to derive arrays of smaller size from large-size systolic arrays based on the partitioning of the large-size arrays into subarrays. In LSGP, the subarrays are clustered one-to-one into the processors of a small-size array, while in LPGS, the subarrays are serially assigned to a reduced-size array. <br /> In this paper, we propose a common methodology for both LSGP and LPGS based on polyhedral partitionings of large-size k-dimensional systolic arrays which are synthesized from n-dimensional uniform recurrences by linear mappings for allocation and timing. In particular, we address the optimization problem of finding optimal piecewise linear timing functions for small-size arrays. These are mappings composed of linear timing functions for the computations of the subarrays. We study a continuous approximation of this problem by passing from piecewise linear to piecewise quasi-linear timing functions. The resultant problem formulation is then a quadratic programming problem which can be solved by standard algorithms for nonlinear optimization problems.}
}

@article{BaZi01,
Author = {N. Suresh Babu and Karl-Heinz Zimmermann},
Title = {Decoding of linear codes over Galois rings.},
Journal = {<em>IEEE Transactions on Information Theory</em>.},
Year = {(2001).},
Volume = {<strong>47</strong>.},
Number = {(4),},
Pages = {1599-1603},
Month = {May},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1109/18.923743},
Howpublished = {01-95 BaZi01 TIT},
Abstract = {We present a method for decoding an arbitrary linear code over a Galois ring ℛ by a process of lifting decoding algorithms for a family of linear codes over a finite field 𝒦 forming an α-element chain, where 𝒦 is the quotient field of ℛ and ℛ has characteristic pα. As a new result, this method also works for linear codes over ℛ which are nonfree ℛ-modules.}
}

@inbook{RBZ00,
Author = {Thomas Rehfinger, N. Suresh Babu and Karl-Heinz Zimmermann},
Title = {New Good Codes via CQuest - A System for the Silicon Search of Linear Codes.},
Year = {(2000).},
Pages = {294-306},
Month = {July},
Note = {khzimmermann, AEG},
Editor = {In A. Betten, A. Kohnert, R. Laue and A. Wassermann (Eds.)},
Publisher = {Springer:},
Isbn = {10.1007/978-3-642-59448-9_19},
Howpublished = {00-95 RBZ00 Springer},
Booktitle = {<em>Algebraic Combinatorics and Applications</em>},
Abstract = {We describe a software tool called CQUest which has been designed for the generation and manipulation of code tables. CQUest handles one code table for each alphabet. It supports two kinds of operations for the manipulation of code tables: code modifications and code combinations. CQUest provides an interpreter for interactive use. Some new good quaternary codes obtained by CQUest are described.}
}

@article{AcZi00,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {Finding Quadratic Schedules for Affine Recurrence Equations Via Nonsmooth Optimization.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(2000).},
Volume = {<strong>25</strong>.},
Number = {(3),},
Pages = {235-260},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1023/A:1008139706909},
Howpublished = {00-90 AcZi00 JVLSI},
Abstract = {Frequently, affine recurrence equations can be scheduled more efficiently by quadratic scheduling functions than by linear scheduling functions. In this paper, the problem of finding optimal quadratic schedules for affine recurrence equations is formulated as a convex nonsmooth programming problem. In particular, sufficient constraints for causality are used generalizing Lamport's condition. In this way, the presented problem formulation becomes independent of the problem size. The research tool AQUAD is described implementing this problem formulation. Several nontrivial examples demonstrate that AQUAD can be effectively used to calculate quadratic schedules for affine recurrence equations. Finally, it is shown how array processors can be synthesized from affine recurrence equations which are scheduled by quadratic functions with a singular Hessian matrix.}
}

@inproceedings{RBZ99,
Author = {Thomas Rehfinger, N. Suresh Babu and Karl-Heinz Zimmermann},
Title = {Parallelizing the Search for Good Linear Codes.},
Year = {(1999).},
Pages = {203-210},
Month = {October},
Note = {khzimmermann, AEG},
Address = {Jena / Germany},
Howpublished = {99-95 RBZ99 ARCS},
Booktitle = {<em>In Proceedings of Workshop zur Architektur von Rechensystemen</em>}
}

@book{BFK+98,
Author = {Anton Betten, Harald Fripertinger, Adalbert Kerber, Alfred Wassermann and Karl-Heinz Zimmermann},
Title = {Codierungstheorie - Konstruktion und Anwendung linearer Codes.},
Year = {(1998).},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/978-3-642-58973-7},
Howpublished = {98-90 BFK+98 Springer},
Abstract = {Eine Einführung in die Theorie der linearen Codes, in der zyklische Codes besonders ausführlich behandelt werden. Großer Wert wird auch auf computerunterstützte Methoden gelegt, insbesondere für die Bestimmung der Minimaldistanz linearer Codes, für die Abzählung der Isometrieklassen linearer Codes sowie Blockcodes und für die Erzeugung von Repräsentantensystemen dieser Klassen. <br /> Das Buch wendet sich an Studenten und Wissenschaftler der Informatik, Mathematik und Elektrotechnik sowie an Fachleute in der Praxis.}
}

@mastersthesis{Falk98,
Author = {Heiko Falk},
Title = {Hardware Partitioning for Prototype Boards (in German).},
Year = {(1998).},
Month = {August},
Note = {hfalk, ESD},
Series = {19980812-mscthesis-falk.pdf},
Address = {Dortmund / Germany},
Howpublished = {98-80 Falk Diploma},
Type = {Diploma Thesis},
School = {University of Dortmund},
Institution = {Faculty of Computer Science},
Abstract = {The diploma thesis deals with the problem to partition complex hardware designs for several FPGAs during HW/SW co-design. Using genetic algorithms, a partitioning method was realized for Xilinx FPGAs that achieves a higher quality than most other published approaches.}
}

@article{ZiAc98,
Author = {Karl-Heinz Zimmermann and Wolfgang Achtziger},
Title = {On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(1998).},
Volume = {<strong>19</strong>.},
Number = {(1),},
Pages = {19-38},
Month = {May},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1023/A:1008008231304},
Howpublished = {98-85 ZiAc98 JVLSI},
Abstract = {Many important algorithms can be described by n-dimensional uniform recurrences. The computations are then indexed by integral vectors of length n and the data dependencies between computations can be described by the difference vector of the corresponding indexes which are independent of the indexes. This paper addresses the following optimization problem: Given an n-dimensional uniform recurrence whose computation indexes are mapped by a linear function onto the processors of an array processor embedded in k-space (1 ≤ k ≤ n). Find an optimal linear function for the computation indexes. We study a continuous approximation of this problem by passing from linear to quasi-linear timing functions. The resultant problem formulation is then a quadratic programming problem which can be solved by standard algorithms for quadratic or general nonlinear optimization problems. We demonstrate the effectiveness of our approach by several nontrivial test examples.}
}

@techreport{AcZi98,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {Computing time-optimal quadratic schedules for affine recurrence equations.},
Year = {(1998).},
Number = {(243),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {98-95 AcZi98 Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@article{Zimm97,
Author = {Karl-Heinz Zimmermann},
Title = {A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(1997).},
Volume = {<strong>17</strong>.},
Number = {(1),},
Pages = {21-41},
Month = {September},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1023/A:1007944932429},
Howpublished = {97-85 Zimm97 JVLSI},
Abstract = {Various methods for the synthesis of systolic arrays from signal and image processing algorithms have been developed in the past few years. In this paper, we propose a technique for the partitioning problem, the problem to synthesize systolic arrays whose size does not match the problem size. Our technique generalizes most of the known lattice-based approaches to the partitioning problem and combines the multiprojection method for the synthesis of systolic arrays with the locally sequential-globally parallel (LSGP) and locally parallel-globally sequential (LPGS) partitioning schemes. Starting from (1) a k-dimensional large-size systolic array obtained from a system of n-dimensional uniform recurrences by a space-time transformation and (2) an arbitrary lattice in k-space inducing a partitioning of the array into subarrays, a small-size systolic array with a scalar-valued system clock is constructed via the LSGP or LPGS paradigm. In particular, the allocation function for the small-size array can be written in closed form and the timing function is obtained from timing functions for the subdomains, the set of operations performed by the subarrays, by simple greedy algorithms. In this way, the problem of finding optimal timing functions can in various cases be reduced to finding optimal timing functions for the subdomains. For problems of large size, these greedy algorithms seem to be preferable when compared with existing integer or non-convex programming formulations for finding (sub-)optimal timing functions. We also provide some new results, a necessary and sufficient condition for the existence of counter data flow, a formal relationship between partitionings of processor space and index space of the uniform recurrences in terms of counter data flow, and the structural equivalence between the lattice-based LSGP and LPGS schemes applied to the partitioning of index and processor space.}
}

@article{ZiAc97,
Author = {Karl-Heinz Zimmermann and Wolfgang Achtziger},
Title = {Finding Space-Time Transformations for Uniform Recurrences via Branching Parametric Linear Programming.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(1997).},
Volume = {<strong>15</strong>.},
Number = {(3),},
Pages = {259-274},
Month = {March},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1023/A:1007963228049},
Howpublished = {97-90 ZiAc97 JVLSI},
Abstract = {Many important algorithms in signal and image processing can be described by uniform recurrences. A common method for the synthesis of systolic arrays from uniform recurrences is based on space-time transformations each of which consisting of two linear mappings, an allocation and a timing function. In this paper, we address the problem of finding space-time transformations which are time-optimal or at least nearly time-optimal. For a given allocation function, a continuous relaxation of this problem is studied by passing from linear to quasi-linear timing functions. A parametrized linear programming formulation is provided for finding quasi-linear timing functions. The solution of each such linear problem, however, depends on the basis representation of the null space of the allocation function. Therefore, a branching approach is proposed for finding quasi-linear timing functions which are optimal or have at least low latency. It will be demonstrated by several large test examples that branching into hundreds or even thousands of linear subproblems can be computed with reasonable effort and often leads to an optimum linear timing function.}
}

@inproceedings{AcZi97,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {Optimal Polynomial Schedules: An Approach via Non-smooth Optimization.},
Year = {(1997).},
Month = {February},
Note = {khzimmermann, AEG},
Address = {Zurich / Switzerland},
Howpublished = {97-95 AcZi97 ARS},
Booktitle = {<em>In Proceedings of the First International Workshop on Approximate Reasoning in Scheduling (ARS)</em>}
}

@article{Zimm96b,
Author = {Karl-Heinz Zimmermann},
Title = {Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(1996).},
Volume = {<strong>12</strong>.},
Number = {(2),},
Pages = {187-202},
Month = {May},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/BF00924526},
Howpublished = {96-55 Zimm96b JVLSI},
Abstract = {We propose two methods for the synthesis of systolic arrays from uniform recurrence equations. First, we discuss a synthesis method for mappingn-dimensional uniform recurrence equations ontok-dimensional systolic arrays with a two-dimensional system clock. In this method we are led by the idea that all space-time conflicts caused by a scalar valued causal timing function and an allocation function can be rule out by a second scalar valued timing function. Stacking both timing functions yields a two-dimensional clock. Second, we develop a method to synthesizek-dimensional arrays with a scalar valued clock from a large subclass ofn-dimensional uniform recurrence equations containing important algorithms from signal and image processing. This method is based on a decomposition of the domain of the uniform recurrence equations into subdomains according to a given procesor allocation which allows the construction of a timing function for the whole domain from timing functions for the subdomains. In this way, the problem of finding optimal timing functions is reduced to finding optimal functions for the subdomains which are usually easier to establish. This synthesis method exhibits simplicity but its drawback lies in its limited applicability.}
}

@article{Zimm96a,
Author = {Karl-Heinz Zimmermann},
Title = {On generalizations of repeated-root cyclic codes.},
Journal = {<em>IEEE Transactions on Information Theory</em>.},
Year = {(1996).},
Volume = {<strong>42</strong>.},
Number = {(2),},
Pages = {641-649},
Month = {March},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1109/18.485736},
Howpublished = {96-65 Zimm96a TIT},
Abstract = {We first consider repeated-root cyclic codes, i.e., cyclic codes whose block length is divisible by the characteristic of the underlying field. It is well known that the formula for the minimum distance of repeated-root cyclic codes is similar to that for generalized concatenated codes. We show that indecomposable repeated-root cyclic codes are product codes and that the minimum weight of each repeated-root cyclic code is attained by one of its subcodes being equivalent to a product code. We then generalize the coding theoretical results on repeated-root cyclic codes to a larger class of left ideals in group algebra Fpm𝒢 defined on non-Abelian groups, namely, groups 𝒢 containing a normal cyclic Sylow p-subgroup. We show that a class of these codes compares reasonably to (shortened) generalized Reed-Muller codes over the primes and finally indicate by the special linear group SL<sub>2</sub>(F<sub>p</sub>) how a further generalization may in principle be settled.}
}

@inproceedings{ZiAc96b,
Author = {Karl-Heinz Zimmermann and Wolfgang Achtziger},
Title = {Synthesizing Regular Arrays from Single Affine Recurrences via Quadratic and Branching Parametric Linear Programming.},
Year = {(1996).},
Pages = {224-231},
Month = {September},
Note = {khzimmermann, AEG},
Address = {Berlin / Germany},
Howpublished = {96-50 ZiAc96b Parcella},
Booktitle = {<em>In Proceedings of the 7th International Workshop on Parallel Processing by Cellular Automata and Arrays (Parcella)</em>}
}

@techreport{ZiAc96a,
Author = {Karl-Heinz Zimmermann and Wolfgang Achtziger},
Title = {Synthesizing regular arrays from affine recurrences via quadratic and branching parametric linear programming.},
Year = {(1996).},
Number = {(174),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {96-85 ZiAc96a Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@inproceedings{AcZi96f,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {A branching linear programming approach for the mapping of systems of n-dimensional affine recurrences onto k-dimensional systolic arrays.},
Year = {(1996).},
Pages = {247-259},
Month = {April},
Note = {khzimmermann, AEG},
Address = {Singapore},
Howpublished = {96-60 AcZi96f PASA},
Booktitle = {<em>In Proceedings of the 4th Workshop on Parallel Systems and Algorithms</em>}
}

@techreport{AcZi96e,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {On time optimal implementation of uniform recurrences onto array processors via quadratic programming.},
Year = {(1996).},
Number = {(204),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {96-70 AcZi96e Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@techreport{AcZi96d,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {On optimal piecewise linear schedules for LSPG- and LPGS-partitionings of array processors via quadratic programming.},
Year = {(1996).},
Number = {(202),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {96-75 AcZi96d Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@techreport{AcZi96c,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {The scheduling problem for recurrence equations.},
Year = {(1996).},
Number = {(200),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {96-80 AcZi96c Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@techreport{AcZi96b,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {A branching linear programming approach for the mapping of systems of n-dimensional affine recurrences onto k-dimensional systolic arrays.},
Year = {(1996).},
Number = {(172),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {96-90 AcZi96b Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@techreport{AcZi96a,
Author = {Wolfgang Achtziger and Karl-Heinz Zimmermann},
Title = {Finding space-time transformations for uniform recurrences via branching parametric linear programming.},
Year = {(1996).},
Number = {(168),},
Note = {khzimmermann, AEG},
Address = {Erlangen / Germany},
Howpublished = {96-95 AcZi96a Erlangen},
Type = {Technical Report},
School = {University of Erlangen Nuermberg},
Institution = {Institute of Applied Mathematics}
}

@inproceedings{Zimm95,
Author = {Karl-Heinz Zimmermann},
Title = {Hecke modules as linear block codes and block m-PSK modulation codes.},
Year = {(1995).},
Pages = {247-259},
Month = {September},
Note = {khzimmermann, AEG},
Address = {Whistler / Canada},
Isbn = {10.1109/ISIT.1995.550482},
Howpublished = {95-90 Zimm95 IT},
Booktitle = {<em>In Proceedings of the IEEE International Symposium on Information Theory</em>},
Abstract = {We discuss the error correction capabilities of a class of Hecke modules as linear codes and free linear block m-PSK modulation codes. We provide an introduction to the study of modules for a Hecke algebra (of type A) as linear codes for the Hamming and the Euclidean metric. These modules are called Hecke modules and play an important role in another branch of mathematics, representation theory of groups and algebras. We first introduce a class of Hecke modules in a purely combinatorial manner. In particular, we provide a basis for each of these modules which can be easily calculated by a computer.}
}

@article{LiZi95,
Author = {Robert A. Liebler and Karl-Heinz Zimmermann},
Title = {Combinatorial S<sub>>n</sub>-Modules as Codes.},
Journal = {<em>IEEE Journal of Algebraic Combinatorics</em>.},
Year = {(1995).},
Volume = {<strong>4</strong>.},
Number = {(1),},
Pages = {47-68},
Month = {January},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1023/A:1022485624417},
Howpublished = {95-95 LiZi95 JAC},
Abstract = {Certain ℤSn-modules related to the kernels ofincidence maps between types in the poset defined by the natural productorder on the set of n-tuples with entries from {1, ... ,m} are studied as linear codes (whencoefficients are extended to an arbitrary field K). Theirdimensions and minimal weights are computed. The Specht modules areextremal among these submodules. The minimum weight codewords of theSpecht module are shown to be scalar multiples of polytabloids. Ageneralization of t-design arising from the natural permutationS n-modules labelled by partitions with mparts is introduced. A connection with Reed-Muller codes is noted and acharacteristic free formulation is presented.}
}

@article{LiZi95,
Author = {Robert A. Liebler and Karl-Heinz Zimmermann},
Title = {Combinatorial S<sub>>n</sub>-Modules as Codes.},
Journal = {<em>IEEE Journal of Algebraic Combinatorics</em>.},
Year = {(1995).},
Volume = {<strong>4</strong>.},
Number = {(1),},
Pages = {47-68},
Month = {January},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1023/A:1022485624417},
Howpublished = {95-95 LiZi95 JAC},
Abstract = {Certain â?¤Sn-modules related to the kernels ofincidence maps between types in the poset defined by the natural productorder on the set of n-tuples with entries from {1, ... ,m} are studied as linear codes (whencoefficients are extended to an arbitrary field K). Theirdimensions and minimal weights are computed. The Specht modules areextremal among these submodules. The minimum weight codewords of theSpecht module are shown to be scalar multiples of polytabloids. Ageneralization of t-design arising from the natural permutationS n-modules labelled by partitions with mparts is introduced. A connection with Reed-Muller codes is noted and acharacteristic free formulation is presented.}
}

@article{Zimm94b,
Author = {Karl-Heinz Zimmermann},
Title = {On weight spaces of polynomial representations of the general linear group as linear codes.},
Journal = {<em>Journal of Combinatorial Theory, Series A</em>.},
Year = {(1994).},
Volume = {<strong>67</strong>.},
Number = {(1),},
Pages = {1-22},
Month = {July},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/0097-3165(94)90001-9},
Howpublished = {94-90 Zimm94b JCT},
Abstract = {We provide a basis for the weight spaces of certain polynomial representations of the general linear group introduced by G. James. Then we determine the minimum distance of those weight spaces which have highest error correction capabilities among all the studied weight spaces and derive a new class of completely majority-logic decodable linear codes. Finally, we show that binary Reed-Muller and Simplex codes also occur as weight spaces.}
}

@article{Zimm94a,
Author = {Karl-Heinz Zimmermann},
Title = {Beitr&auml;ge zur algebraischen Codierungstheorie mittels modularer Darstellungstheorie.},
Journal = {<em>Bayreuther Mathematische Schriften</em>.},
Year = {(1994).},
Volume = {<strong>48</strong>.},
Note = {khzimmermann, AEG},
Publisher = {University of Bayreuth:},
Howpublished = {94-95 Zimm94a BMS}
}

@article{Zimm93c,
Author = {Karl-Heinz Zimmermann},
Title = {On the majority decodable distance of codes in filtrations of characteristic p>0.},
Journal = {<em>Archiv der Mathematik</em>.},
Year = {(1993).},
Volume = {<strong>61</strong>.},
Number = {(5),},
Pages = {434-443},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/BF01207542},
Howpublished = {93-80 Zimm93c AM}
}

@article{Zimm93b,
Author = {Karl-Heinz Zimmermann},
Title = {On the decoding of indecomposable binary group codes.},
Journal = {<em>Atti del Seminario Matematico e Fisico dell'Universita di Modena</em>.},
Year = {(1993).},
Volume = {<strong>41</strong>.},
Pages = {445-455},
Note = {khzimmermann, AEG},
Publisher = {University of Modena:},
Howpublished = {93-90 Zimm93b Atti}
}

@inproceedings{Zimm93a,
Author = {Karl-Heinz Zimmermann},
Title = {On the exponent of indecomposable abelian group codes.},
Year = {(1993).},
Pages = {291-295},
Note = {khzimmermann, AEG},
Publisher = {John Wiley & Sons:},
Howpublished = {93-95 Zimm93a CDGT},
Booktitle = {<em>In Proceedings of the Marshall Hall conference on Coding theory, design theory, group theory</em>}
}

@inproceedings{Zimm93a,
Author = {Karl-Heinz Zimmermann},
Title = {On the exponent of indecomposable abelian group codes.},
Year = {(1993).},
Pages = {291-295},
Note = {khzimmermann, AEG},
Publisher = {John Wiley & Sons:},
Howpublished = {93-95 Zimm93a CDGT},
Booktitle = {<em>In Proceedings of the Marshall Hall conference on Coding theory, design theory, group theory</em>}
}

@article{ZLK93,
Author = {Karl-Heinz Zimmermann, Tien-Chien Lee and Sun-Yuan Kung},
Title = {On partitioning and fault tolerance issues for neural array processors.},
Journal = {<em>Journal of Signal Processing Systems</em>.},
Year = {(1993).},
Volume = {<strong>6</strong>.},
Number = {(1),},
Pages = {85-94},
Month = {June},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/BF01581962},
Howpublished = {93-85 ZLK93 JSPS},
Abstract = {In this article, we have studied time-efficient schedule and fault-tolerant design of partitioned array processors for neural networks. First, we have applied the locally-sequential-globally-parallel (LSGP) partitioning scheme to decompose large-size neural network algorithms so that they can be mapped into array processors of smaller size. Then we have derived an optimal latency schedule, i.e., for the same decomposition the schedule outperforms any other schedule, in terms of overall execution time. We have further proposed an algorithm-based fault tolerance (ABFT) method to guarantee higher reliability for the array processor implementation.}
}

@article{Zimm92c,
Author = {Karl-Heinz Zimmermann},
Title = {On a complete decoding scheme for binary radical codes.},
Journal = {<em>Archiv der Mathematik</em>.},
Year = {(1992).},
Volume = {<strong>59</strong>.},
Number = {(5),},
Pages = {513-520},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {Springer:},
Isbn = {10.1007/BF01236047},
Howpublished = {92-85 Zimm92c AM}
}

@article{Zimm92b,
Author = {Karl-Heinz Zimmermann},
Title = {The weight distribution of indecomposable cyclic codes over 2-groups.},
Journal = {<em>Journal of Combinatorial Theory, Series A</em>.},
Year = {(1992).},
Volume = {<strong>60</strong>.},
Number = {(1),},
Pages = {85-103},
Month = {May},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/0097-3165(92)90039-W},
Howpublished = {92-90 Zimm92b JCT},
Abstract = {In this paper, we study a class of codes, the so-called coset group codes, and prove several interesting properties about coset group codes. The indecomposable cyclic codes of length pm over the alphabet GF(pn) can be viewed as coset group codes. From this characterization we firstly obtain the weight distribution of all indecomposable GF(2n)C2m-codes, and secondly the weight distribution of the radical powers of GF(2n)G if G contains a normal cyclic 2-Sylow subgroup.}
}

@inbook{Zimm92a,
Author = {Karl-Heinz Zimmermann},
Title = {An optimal partitioning method for parallel algorithms: LSGP.},
Year = {(1992).},
Pages = {233-266},
Note = {khzimmermann, AEG},
Editor = {In B. Soucek (Eds.)},
Publisher = {John Wiley & Sons:},
Howpublished = {92-95 Zimm92a IRIS},
Booktitle = {<em>Fuzzy, holographic, and parallel intelligence: The sixth-generation breakthrough</em>}
}

@inproceedings{Zimm91c,
Author = {Karl-Heinz Zimmermann},
Title = {On the construction of majority-logic decodable group codes.},
Year = {(1991).},
Pages = {367-377},
Month = {December},
Note = {khzimmermann, AEG},
Address = {Cirencester / United Kingdom},
Howpublished = {91-85 Zimm91c CC},
Booktitle = {<em>In Proceedings of the 3rd IMA International Conference on Cryptography and Coding</em>}
}

@article{Zimm91b,
Author = {Karl-Heinz Zimmermann},
Title = {On indecomposable Abelian codes and their vertices.},
Journal = {<em>IEEE Transactions on Information Theory</em>.},
Year = {(1991).},
Volume = {<strong>37</strong>.},
Number = {(6),},
Pages = {1723-1731},
Month = {November},
Note = {khzimmermann, AEG},
Publisher = {IEEE:},
Isbn = {10.1109/18.104341},
Howpublished = {91-90 Zimm91b TIT},
Abstract = {Indecomposable nonsemisimple Abelian codes are investigated. The author describes all indecomposable Abelian group codes and shows that the minimal distance of such a code M is the product of the minimal distance of a semisimple Abelian group code and the minimal distance of the source module of M. It is illustrated that the minimal distance of every indecomposable Abelian code depends upon its associated vertex.}
}

@article{Zimm91a,
Author = {Karl-Heinz Zimmermann},
Title = {Spechtmoduln als Codes.},
Journal = {<em>S&eacute;minaire Lotharingien de Combinatoire</em>.},
Year = {(1991).},
Volume = {<strong>27</strong>.},
Pages = {101-110},
Month = {July},
Note = {khzimmermann, AEG},
Howpublished = {91-95 Zimm91a SLC}
}

@article{Zimm90,
Author = {Karl-Heinz Zimmermann},
Title = {The theory of acyclic systolic systems.},
Journal = {<em>Journal of Parallel and Distributed Computing</em>.},
Year = {(1990).},
Volume = {<strong>9</strong>.},
Number = {(1),},
Pages = {26-41},
Month = {May},
Note = {khzimmermann, AEG},
Publisher = {Elsevier:},
Isbn = {10.1016/0743-7315(90)90109-3},
Howpublished = {90-95 Zimm90 JPDC},
Abstract = {The topic of this paper is the investigation of semisystolic systems with acyclic interconnection structure. To understand the nature of such systems, a new kind of polyautomaton is introduced which we call pipeline automaton. We study the abilities of pipeline automata with respect to equivalence, isomorphy, and simulation. As a major result a structure theorem concerning the simulation of n-dimensional systolic arrays is proved. From this theorem we derive a method of transforming systolic arrays producing results at the end of each computation into on-the-fly systolic arrays. Important results concerning semisystolic systems like the "Retiming Lemma," the "Cut Theorem," and related theorems are transferred into the context of pipeline automata. The acyclic versions of these theorems can be stated for autonomous systems excluding the I/O behavior with respect to some host computer. Thus large-scale I/O considerations can be omitted. Furthermore these statements can be proved more elegantly within an order-theoretic framework.}
}

@inproceedings{Zimm88,
Author = {Karl-Heinz Zimmermann},
Title = {Pipeline-automata - A model for acyclic systolic systems.},
Year = {(1988).},
Pages = {372-379},
Month = {October},
Note = {khzimmermann, AEG},
Address = {Berlin / Germany},
Isbn = {10.1007/3-540-50647-0_132},
Howpublished = {88-95 Zimm88 Parcella},
Booktitle = {<em>In Proceedings of the 4th International Workshop on Parallel Processing by Cellular Automata and Arrays (Parcella)</em>},
Abstract = {In this paper semisystolic systems with acyclic interconnection structures are investigated. Their underlying acyclic graphs represent partially ordered set diagrams of specific partially ordered sets. To understand the nature of such systems a new kind of polyautomata is introduced which we call pipeline-automata. The dynamical behavior of a pipeline-automaton resembles that of a pipeline. After providing the necessary order theoretic concepts the abilities of pipeline-automata with respect to equivalence, isomorphy and simulation are discussed. Because of their outstanding practical relevancy pipeline-automata with grid like interconnection structures are studied. To demonstrate the power of the formalism introduced, important results about semisystolic systems are transferred into the concept of pipeline-automata. This provides also a new proof of the "Retiming Lemma", which is shorter and even more comprehensible than the original one from Leiserson and Saxe.}
}

@COMMENT{Bibtex file generated on 2026-5-12 with typo3 si_bibtex plugin. Data from https://www.tuhh.de/es/home/publications }