Title: WCET-driven Cache-aware Code Positioning. <em>In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)</em>
Written by: Heiko Falk and Helena Kotthaus
in: October (2011).
Volume: Number:
on pages: 145-154
Series: 20111011-cases-falk.pdf
Address: Taipei / Taiwan
ISBN: 10.1145/2038698.2038722
how published: 11-40 FaKo11 CASES
Type: <strong>Best Paper Candidate</strong>.

Note: hfalk, ESD, WCC

Abstract: Code positioning is a well-known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of code fragments in memory avoids overlapping of cache sets and thus decreases the number of cache conflict misses.<br /> We present a novel cache-aware code positioning optimization driven by worst-case execution time (WCET) information. For this purpose, we introduce a formal cache model based on a conflict graph which is able to capture a broad class of cache architectures. This cache model is combined with a formal WCET timing model, resulting in a cache conflict graph weighted with WCET data. This conflict graph is then exploited by heuristics for code positioning of both basic blocks and entire functions.<br /> Code positioning is able to decrease the accumulated cache misses for a total of 18 real-life benchmarks by 15.5% on average for an automotive processor featuring a 2-way set-associative cache. These cache miss reductions translate to average WCET reductions by 6.1%. For direct-mapped caches, even larger savings of 18.8% (cache misses) and 9.0% (WCET) were achieved.