@inproceedings{BEZWT16,
author = {Andreas Becher, Jorge Echavaria, Daniel Ziener, Stefan Wildermann and Jürgen Teich},
title = {A LUT-Based Approximate Adder.},
year = {2016},
month = {May},
note = {dziener, ESD},
address = {Washington DC / USA},
isbn = {10.1109/FCCM.2016.16},
howpublished = {16-65 BEZWT16 FCCM},
booktitle = {In Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
abstract = {In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.}
}

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