2006

  • Goerschwin Fey.
    Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques.
    Ph.D. Thesis. 2006.


  • Goerschwin Fey and Daniel Große and Rolf Drechsler.
    Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks.
    Design, Automation and Test in Europe (DATE), pages 1225-1226, 2006.


  • Goerschwin Fey and Junhao Shi and Rolf Drechsler.
    Efficiency of multiple-valued encoding in SAT-based ATPG.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 25 (6 pages), 2006.


  • Goerschwin Fey and Junhao Shi and Rolf Drechsler.
    Efficiency of multiple-valued encoding in SAT-based ATPG.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), pages 107-108, 2006.


  • Goerschwin Fey and Sean Safarpour and Andreas Veneris and Rolf Drechsler.
    On the Relation Between Simulation-based and SAT-based Diagnosis.
    Design, Automation and Test in Europe (DATE), pages 1139-1144, 2006.


  • Goerschwin Fey and Tim Warode and Rolf Drechsler.
    Using Structural Learning Techniques in SAT-based ATPG.
    Int'l Workshop on Boolean Problems (IWSBP), pages 63-69, 2006.


  • Stefan Staber and Goerschwin Fey and Roderick Bloem and Rolf Drechsler.
    Automatic Fault Localization for Property Checking.
    IBM Haifa Verification Conference (HVC), pages 50-64, 2006.


2005

  • Andreas Breiter and Goerschwin Fey and Rolf Drechsler.
    Project-Based Learning in Student Teams in Computer Science Education.
    In Facta Universitatis, pages 165-180, 2005.


  • Rolf Drechsler and Goerschwin Fey and Christian Genz and Daniel Große.
    SyCE: An Integrated Environment for System Design in SystemC.
    IEEE Int'l Workshop on Rapid System Prototyping (RSP), pages 258-260, 2005.


  • Rüdiger Ebendt and Goerschwin Fey and Rolf Drechsler.
    Advanced BDD Optimization.
    2005.


  • Goerschwin Fey and Rolf Drechsler.
    Efficient Hierarchical System Debugging for Property Checking.
    IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), pages 41-46, 2005.


  • Goerschwin Fey and Rolf Drechsler (editors).
    FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC.
    2005.


  • Sebastian Kinder and Goerschwin Fey and Rolf Drechsler.
    Controlling the Memory During Manipulation of Word-Level Decision Diagrams.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 250-255, 2005.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke.
    PASSAT: Efficient SAT-based Test Pattern Generation.
    IEEE Annual Symposium on VLSI (ISVLSI), pages 212-217, 2005.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke.
    Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits.
    IEEE Int'l Conference on ASIC (ASICON), 2005.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Juergen Schloeffel and Friedrich Hapke.
    PASSAT: Efficient SAT-based Test Pattern Generation.
    IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), pages 166-173, 2005.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler.
    Bridging Fault Testability of BDD Circuits.
    ASP Design Automation Conference (ASPDAC), pages 188-191, 2005.


  • Sean Safarpour and Goerschwin Fey and Andreas Veneris and Rolf Drechsler.
    Utilizing Don't Care States in SAT-based Bounded Sequential Problems.
    Great Lakes Symp. VLSI (GLS), pages 264-269, 2005.


2004

  • Nicole Drechsler and Mario Hilgemeier and Goerschwin Fey and Rolf Drechsler.
    Disjoint Sum of Product Minimization by Evolutionary Algorithms.
    Applications of Evolutionary Computing: EvoWorkshops, pages 198-207, 2004.


  • Rolf Drechsler and Junhao Shi and Goerschwin Fey.
    Synthesis of Fully Testable Circuits from BDDs.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 440-443, 2004.


  • Goerschwin Fey and Rolf Drechsler.
    Improving Simulation-Based Verification by Means of Formal Methods.
    ASP Design Automation Conference (ASPDAC), pages 640-643, 2004.


  • Goerschwin Fey and Rolf Drechsler.
    Visualization of Diagnosis Results for Design Debugging.
    Internatinal Workshop on Post-Binary ULSI Systems (ULSIWS), pages 1-2, 2004.


  • Rolf Drechsler and Goerschwin Fey.
    Design Understanding by Automatic Property Generation.
    Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pages 274-281, 2004.


  • Goerschwin Fey and Rolf Drechsler and Maciej Ciesielski.
    Algorithms for Taylor Expansion Diagrams.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 235-240, 2004.


  • Goerschwin Fey and Daniel Große and Tim Cassens and Christian Genz and Tim Warode and Rolf Drechsler.
    ParSyC: An Efficient SystemC Parser.
    Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pages 148-154, 2004.


  • Goerschwin Fey and Junhao Shi and Rolf Drechsler.
    BDD Circuit Optimization for Path Delay Fault Testability.
    EUROMICRO Symposium on Digital System Design (DSD), pages 162-172, 2004.


  • Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey.
    Cost-efficient Block Verification for a UMTS Up-link Chip-rate Coprocessor.
    Design, Automation and Test in Europe (DATE), pages 162-167, 2004.


2003

  • Rolf Drechsler and Junhao Shi and Goerschwin Fey.
    MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits.
    Great Lakes Symp. VLSI (GLS), pages 80-83, 2003.


  • Goerschwin Fey and Rolf Drechsler.
    A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization.
    Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pages 54-60, 2003.


  • Goerschwin Fey and Rolf Drechsler.
    Finding Good Counter-Examples to Aid Design Verification.
    ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE), pages 51-52, 2003.


  • Goerschwin Fey and Sebastian Kinder and Rolf Drechsler.
    Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 361-366, 2003.


  • Goerschwin Fey and Junhao Shi and Rolf Drechsler.
    BDD Circuit Optimization for Path Delay Fault-Testability.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2003.


  • Daniel Große and Goerschwin Fey and Rolf Drechsler.
    Modeling Multi-Valued Circuits in SystemC.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 281-286, 2003.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler.
    BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
    Asian Test Symposium (ATS), pages 290-293, 2003.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler.
    BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
    IEEE European Test Workshop (ETW), pages 109-110, 2003.


  • Junhao Shi and Goerschwin Fey and Rolf Drechsler.
    Random Pattern Testability of Circuits Derived from BDDs.
    IEEE Workshop on RTL and High Level Testing (WRTLT), pages 70-78, 2003.


  • Klaus Winkelmann and Hans-Joachim Trylus and Dominik Stoffel and Goerschwin Fey.
    Cost-efficient Formal Block Verification for ASIC Design.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 184-188, 2003.


2002

  • Goerschwin Fey and Rolf Drechsler.
    Minimizing the Number of Paths in BDDs.
    Int'l Workshop on Boolean Problems (IWSBP), 2002.


  • Goerschwin Fey and Rolf Drechsler.
    Minimizing the Number of Paths in BDDs.
    Symposium on Integrated Circuits and Systems Design (SBCCI), pages 359-364, 2002.


  • Goerschwin Fey and Rolf Drechsler.
    Utilizing BDDs for Disjoint SOP Minimization.
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pages 306-309, 2002.


  • Jörg Ritter and Goerschwin Fey and Paul Molitor.
    SPIHT implemented in a XC4000 device.
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pages 239-242, 2002.


2001

  • Goerschwin Fey.
    Set Partitioning in Hierarchical Trees: eine FPGA-Implementierung.
    Diploma Thesis 2001.


Displaying results 201 to 242 out of 242

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