2012

  • Goerschwin Fey.
    Assessing System Vulnerability using Formal Verification Techniques.
    Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS) - Revised Selected Papers, pages 47-56, 2012.


  • Finder, Alexander and Fey, Görschwin.
    Evaluating Debugging Algorithms from a Qualitative Perspective.
    System Specification and Design Languages - Selected Contributions from FDL 2010, pages 21-36, 2012.


  • Stefan Frehse and Goerschwin Fey and Eli Arbel and Karen Yorav and Rolf Drechsler.
    Complete and Effective Robustness Checking by Means of Interpolation.
    Formal Methods in Computer-Aided Design (FMCAD), pages 82-90, 2012.


  • Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (editors).
    Verifying Reliability (Dagstuhl Seminar 12341).
    In Dagstuhl Reports, pages 57-73, 2012.
    [doi: http://dx.doi.org/10.4230/DagRep.2.8.57]

  • Goerschwin Fey and Masahiro Fujita and Natasha Miskov-Zivanov and Kaushik Roy and Matteo Sonza Reorda (Organizers).
    Verifying Reliability (Dagstuhl Seminar 12341).
    In Dagstuhl Reports, 2012.


  • Stefan Frehse and Heinz Riener and Goerschwin Fey.
    Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 90-96, 2012.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Automated Feature Localization for Hardware Designs using Coverage Metrics.
    Design Automation Conference (DAC), pages 941-946, 2012.


  • Jan Malburg and Alexander Finder and Goerschwin Fey.
    Automated Feature Localization for Hardware Designs using Coverage Metrics.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012.


  • Jaan Raik (Organizer).
    Panel: Can RTL test techniques be applied to software?.
    2012.


  • Heinz Riener and Goerschwin Fey.
    Model-Based Diagnosis versus Error Explanation.
    ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE), pages 43-52, 2012.


  • Heinz Riener and Goerschwin Fey.
    FAUST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.
    International SPIN Workshop on Model Checking of Software (SPIN), pages 234-240, 2012.


  • Heinz Riener and Goerschwin Fey.
    Model-Based Diagnosis versus Error Explanation.
    International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES), 2012.


  • Mathias Soeken and Heinz Riener and Robert Wille and Goerschwin Fey and Rolf Drechsler.
    Verification of Embedded Systems Using Modeling and Implementation Languages.
    International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs), pages 67-72, 2012.


2011

  • Mehdi Dehbashi and Goerschwin Fey.
    Automated Post-Silicon Debugging of Design Bugs.
    System, Software, SoC and Silcon Debug Conference (S4D), pages 67-71, 2011.


  • Mehdi Dehbashi and André Sülflow and Goerschwin Fey.
    Automated Design Debugging in a Testbench-Based Verification Environment.
    EUROMICRO Symposium on Digital System Design (DSD), pages 479-486, 2011.


  • Goerschwin Fey.
    Orchestrated Multi-Level Information Flow Analysis to Understand SoCs.
    Design Automation Conference (DAC), pages 284-285, 2011.


  • Goerschwin Fey.
    Assessing System Vulnerability using Formal Verification Techniques.
    Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS), 2011.


  • Stefan Frehse and Finn Haedicke and Melanie Diepenbeck and Goerschwin Fey and Rolf Drechsler.
    Hochoptimierter Ablauf zur Robustheitsprüfung.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 35-42, 2011.


  • Alexander Finder and André Sülflow and Goerschwin Fey.
    Latency Analysis for Sequential Circuits.
    IEEE European Test Symposium (ETS), pages 129-134, 2011.
    [doi: 10.1109/ETS.2011.34]

  • Alexander Finder and André Sülflow and Goerschwin Fey.
    Latency Analysis for Sequential Circuits.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), pages 119-124, 2011.


  • Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler.
    Effective Robustness Analysis using Bounded Model Checking Techniques.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 1239-1252, 2011.
    [doi: 10.1109/TCAD.2011.2120950]

  • Daniel Große and Goerschwin Fey and Rolf Drechsler.
    Enhanced Formal Verification Flow for Circuits Integrating Debugging.
    Design and Test Technology for Dependable Systems-on-Chip, pages 119-129, 2011.


  • Finn Haedicke and Stefan Frehse and Goerschwin Fey and Daniel Große and Rolf Drechsler.
    metaSMT: Focus on Your Application not on Solver Integration.
    Int'l Workshop on Design and Implementation of Formal Tools and Systems (DIFTS), pages 22-29, 2011.


  • Heinz Riener and Roderick Bloem and Goerschwin Fey.
    Test Case Generation from Mutants using Model Checking Techniques.
    Mutation, pages 388-397, 2011.


  • Mathias Soeken and Ulrich Kühne and Martin Freibothe and Goerschwin Fey and Rolf Drechsler.
    Towards Automatic Property Generation for the Formal Verification of Bus Bridges.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 417-422, 2011.


  • Mathias Soeken and Ulrich Kühne and Martin Freibothe and Goerschwin Fey and Rolf Drechsler.
    Towards Automatic Property Generation for the Formal Verification of Bus Bridges.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011.


2010

  • Rolf Drechsler and Goerschwin Fey.
    Formal verification meets robustness checking - techniques and challenges (Tutorial).
    2010.


  • Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Rolf Drechsler.
    MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.
    In Journal of Electronic Testing: Theory and Applications (JETTA), pages 307-322, 2010.


  • Goerschwin Fey (Organizer).
    Design Closure for Reliability.
    Design Automation Conference (DAC), 2010.


  • Stefan Frehse and Goerschwin Fey.
    Kompositionelle Formale Robustheitsprüfung.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 73-74, 2010.


  • Alexander Finder and Goerschwin Fey.
    Evaluating Debugging Algorithms from a Qualitative Perspective.
    Forum on Specification and Design Languages (FDL), 2010.


  • Alexander Finder and Goerschwin Fey.
    Evaluating Debugging Algorithms from a Qualitative Perspective.
    Int'l Workshop on Boolean Problems (IWSBP), 2010.


  • Stefan Frehse and Goerschwin Fey and Rolf Drechsler.
    A Better-Than-Worst-Case Robustness Measure.
    IEEE Int'l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 78-83, 2010.


  • Stefan Frehse and Goerschwin Fey and Rolf Drechsler.
    A Better-Than-Worst-Case Robustness Measure.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), pages 19-24, 2010.


  • Stefan Frehse and Goerschwin Fey and Rolf Drechsler.
    A Better-Than-Worst-Case Robustness Measure.
    Int'l Test Conference (ITC), 2010.


  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler.
    RobuCheck: A Robustness Checker for Digital Circuits.
    EUROMICRO Symposium on Digital System Design (DSD), pages 226-231, 2010.


  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler.
    RobuCheck: A Robustness Checker for Digital Circuits.
    Workshop on Dynamic Aspects in Dependability Model for Fault-Tolerant Systems (DYADEM-FTS), pages 37-38, 2010.


  • Goerschwin Fey and André Sülflow and Rolf Drechsler.
    Towards Unifying Localization and Explanation for Automated Debugging.
    International Workshop on Microprocessor Test and Verification (MTV), pages 3-8, 2010.


  • Goerschwin Fey and André Sülflow and Stefan Frehse and Rolf Drechsler.
    Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen.
    In it - Information Technology, pages 216-222, 2010.


  • Finn Haedicke and Bijan Alizadeh and Goerschwin Fey and Masahiro Fujita and Rolf Drechsler.
    Polynomial Datapath Optimization using Constraint Solving and Formal Modelling.
    IEEE/ACM Int'l Conf. on CAD (ICCAD), pages 756-761, 2010.


  • André Sülflow and Goerschwin Fey and Rolf Drechsler.
    Using QBF to Increase Accuracy of SAT-Based Debugging.
    IEEE Int'l Symposium on Circuits and Systems (ISCAS), pages 641-644, 2010.


  • André Sülflow and Goerschwin Fey and Rolf Drechsler.
    Bounded Fault Tolerance Checking (Invited Talk).
    Forum on Specification and Design Languages (FDL), 2010.


2009

  • Dominique Borrione and Rolf Drechsler and Emmanuelle Encrenaz-Tiphene and Goerschwin Fey.
    Formal and Semi-formal Methods for Correctness and Robustness (Tutorial).
    2009.


  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille.
    Test Pattern Generation using Boolean Proof Engines.
    2009.


  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille.
    Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern.
    In it - Information Technology, pages 102-111, 2009.


  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Daniel Tille.
    SAT-based Automatic Test Pattern Generation.
    Evolutionary Test Generation Dagstuhl-Seminar, 2009.


  • Rolf Drechsler and Goerschwin Fey.
    Formale Verifikation und Robustheit (Tutorial).
    2009.


  • Goerschwin Fey.
    Deterministic Algorithms for ATPG under Leakage Constraints.
    Asian Test Symposium (ATS), pages 313-316, 2009.


  • Goerschwin Fey.
    Algorithms for ATPG under Leakage Constraints.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), pages 91-96, 2009.


  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler.
    Robustness Check for Multiple Faults using Formal Techniques.
    EUROMICRO Symposium on Digital System Design (DSD), pages 85-90, 2009.


  • Stefan Frehse and Goerschwin Fey and André Sülflow and Rolf Drechsler.
    Robustness Check for Multiple Faults using Formal Techniques.
    Workshop on Constraints in Formal Verification (CFV), 2009.


  • Goerschwin Fey and André Sülflow and Rolf Drechsler.
    Computing Bounds for Fault Tolerance using Formal Techniques.
    Design Automation Conference (DAC), pages 190-195, 2009.


  • Toru Nakura and Yutaro Tatemura and Goerschwin Fey and Makoto Ikeda and Satoshi Komatsu and Kunihiro Asada.
    SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults.
    European Conference on Circuit Theory and Design (ECCTD), pages 643-647, 2009.


  • Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke.
    Advanced Verification by Automatic Property Generation.
    In IET Computers and Digital Techniques, pages 338-353, 2009.


  • André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler.
    Increasing the Accuracy of SAT-based Debugging.
    Design, Automation and Test in Europe (DATE), pages 1326-1331, 2009.


  • André Sülflow and Goerschwin Fey and Cecile Braunstein and Ulrich Kühne and Rolf Drechsler.
    Increasing the Accuracy of SAT-based Debugging.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009.


  • André Sülflow and Goerschwin Fey and Rolf Drechsler.
    Using QBF to Increase Accuracy of SAT-based Debugging.
    Workshop on Constraints in Formal Verification (CFV), 2009.


  • André Sülflow and Stefan Frehse and Goerschwin Fey and Rolf Drechsler.
    Anwendungsbezogene Analyse der Robustheit von digitalen Schaltungen.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 45-52, 2009.


  • André Sülflow and Ulrich Kühne and Goerschwin Fey and Daniel Große and Rolf Drechsler.
    WoLFram - A Word Level Framework for Formal Verification.
    IEEE/IFIP Int'l Symposium on Rapid System Prototyping (RSP), pages 11-17, 2009.


  • André Sülflow and Robert Wille and Goerschwin Fey and Rolf Drechsler.
    Evaluation of Cardinality Constraints on SMT-based Debugging.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 298-303, 2009.


  • Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler.
    SWORD: A SAT like prover using word level information.
    VLSI-SoC: Advanced Topics on Systems on a Chip, pages 175-192, 2009.


2008

  • Rolf Drechsler and Stephan Eggersglüß and Goerschwin Fey and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel and Daniel Tille.
    On Acceleration of SAT-based ATPG for Industrial Designs.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 1329-1333, 2008.


  • Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler.
    On the Construction of Small Fully Testable Circuits with Low Depth.
    In Microprocessors and Microsystems (MICPRO), pages 263-269, 2008.


  • Goerschwin Fey and Rolf Drechsler.
    A Basis for Formal Robustness Checking.
    Int'l Symposium on Quality Electronic Design (ISQED), pages 784-789, 2008.


  • Goerschwin Fey and Rolf Drechsler.
    Robustness and Usability in Modern Design Flows.
    2008.


  • Goerschwin Fey and Rolf Drechsler.
    Synthesis for Detection of Transient Faults.
    IEICE Workshop on Dependable Computing, pages 161-166, 2008.


  • Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita.
    Targeting Leakage Constraints during ATPG.
    Asian Test Symposium (ATS), pages 225-230, 2008.


  • Goerschwin Fey and Satoshi Komatsu and Yasuo Furukawa and Masahiro Fujita.
    Targeting Leakage Constraints during ATPG.
    IEEE Int'l Workshop on Silicon Debug and Diagnosis (SDD), 2008.


  • Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler.
    Automatic Fault Localization for Property Checking.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 1138-1149, 2008.


  • Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler.
    Automatic Fault Localization for Property Checking.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 1138-1149, 2008.


  • Goerschwin Fey and André Sülflow and Stefan Frehse and Ulrich Kühne and Rolf Drechsler.
    Formaler Nachweis der Fehlertoleranz von Schaltkreisen.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 75-82, 2008.


  • Frank Rogin and Thomas Klotz and Goerschwin Fey and Rolf Drechsler and Steffen Rülke.
    Automatic Generation of Complex Properties for Hardware Designs.
    Design, Automation and Test in Europe (DATE), pages 545-548, 2008.


  • Frank Rogin and Thomas Klotz and Steffen Rülke and Goerschwin Fey and Rolf Drechsler.
    Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs.
    Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS), 2008.


  • André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler.
    Using Unsatisfiable Cores to Debug Multiple Design Errors.
    Great Lakes Symp. VLSI (GLS), pages 77-82, 2008.


  • André Sülflow and Goerschwin Fey and Roderick Bloem and Rolf Drechsler.
    Debugging Design Errors by Using Unsatisfiable Cores.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 159-168, 2008.


  • André Sülflow and Goerschwin Fey and Rolf Drechsler.
    Experimental Studies on SMT-based Debugging.
    IEEE Workshop on RTL and High Level Testing (WRTLT), pages 93-98, 2008.


  • André Sülflow and Goerschwin Fey and Stefan Frehse and Ulrich Kühne and Rolf Drechsler.
    Computing Bounds for Fault Tolerance using Formal Techniques.
    Workshop on Design for Reliability and Variability (DRV), 2008.


  • Robert Wille and Goerschwin Fey and Marc Messing and Gerhard Angst and Lothar Linhard and Rolf Drechsler.
    Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.
    EUROMICRO Symposium on Digital System Design (DSD), pages 542-549, 2008.


2007

  • Rolf Drechsler and Goerschwin Fey and Sebastian Kinder.
    An Integrated Approach for Combining BDDs and SAT Provers.
    In Facta Universitatis, pages 415-436, 2007.


  • Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel.
    Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
    ACM/IEEE Int'l Conference on Formal Methods and Models for Codesign (MEMOCODE), pages 181-187, 2007.


  • Stephan Eggersglüß and Goerschwin Fey and Rolf Drechsler.
    SAT-based ATPG for Path Delay Faults in Sequential Circuits.
    IEEE Int'l Symposium on Circuits and Systems (ISCAS), pages 3671-3674, 2007.


  • Goerschwin Fey and Anna Bernasconi and Valentina Ciriani and Rolf Drechsler.
    On the Construction of Small Fully Testable Circuits with Low Depth.
    EUROMICRO Symposium on Digital System Design (DSD), pages 563-569, 2007.


  • Goerschwin Fey and Rolf Drechsler.
    Ein formaler Ansatz zum Robustheitsnachweis.
    GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE), pages 101-108, 2007.


  • Goerschwin Fey and Rolf Drechsler.
    Formal Robustness Checking.
    Workshop on Constraints in Formal Verification (CFV), 2007.


  • Goerschwin Fey.
    Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques.
    Ausgezeichnete Informatikdissertationen 2006, pages 29-38, 2007.


  • Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Robert Wille and Rolf Drechsler.
    Formal Verification on the Word Level using SAT-like Proof Techniques.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007.


  • Goerschwin Fey and Tim Warode and Rolf Drechsler.
    Using Structural Learning Techniques in SAT-based ATPG.
    VLSI Design Conference, pages 69-74, 2007.


  • Daniel Große and Goerschwin Fey and Rolf Drechsler (editors).
    SATRIX - Algorithmen für Boolesche Erfüllbarkeit.
    2007.


  • Sebastian Kinder and Goerschwin Fey and Rolf Drechsler.
    Estimating the Quality of AND-EXOR Optimization Results.
    Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design, 2007.


  • André Sülflow and Goerschwin Fey and Rolf Drechsler.
    Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007.


  • Stephan Eggersglüß and Daniel Tille and Goerschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel.
    Experimental Studies on SAT-based ATPG for Gate Delay Faults.
    IEEE Int'l Symposium on Multi-Valued Logic (ISMVL), pages 6 (6 pages), 2007.


  • Daniel Tille and Stephan Eggersglüß and Görschwin Fey and Rolf Drechsler and Andreas Glowatz and Friedrich Hapke and Juergen Schloeffel.
    Studies on Integrating SAT-based ATPG in an Industrial Environment.
    GI/GMM/ITG-Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), 2007.


  • Daniel Tille and Goerschwin Fey and Rolf Drechsler.
    Instance Generation for SAT-based ATPG.
    IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), 2007.


  • Robert Wille and Goerschwin Fey and Rolf Drechsler.
    Building Free Binary Decision Diagrams Using SAT Solvers.
    Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design, 2007.


  • Robert Wille and Goerschwin Fey and Rolf Drechsler.
    Building Free Binary Decision Diagrams Using SAT Solvers.
    In Facta Universitatis, pages 381-394, 2007.


  • Robert Wille and Goerschwin Fey and Daniel Große and Stephan Eggersglüß and Rolf Drechsler.
    SWORD: A SAT like prover using word level information.
    IEEE/IFIP Int'l Conference on VLSI and System-on-Chip (VLSI-SoC), pages 88-93, 2007.


2006

  • Rolf Drechsler and Goerschwin Fey.
    Automatic Test Pattern Generation.
    School on Formal Methods for Hardware Verification, pages 30-55, 2006.


  • Rolf Drechsler and Goerschwin Fey and Sebastian Kinder.
    An Integrated Approach for Combining BDD and SAT Provers.
    VLSI Design Conference, pages 237-242, 2006.


  • Goerschwin Fey and Rolf Drechsler.
    SAT-based Calculation of Source Code Coverage for BMC.
    ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), pages 163-170, 2006.


  • Goerschwin Fey and Rolf Drechsler.
    Minimizing the Number of Paths in BDDs - Theory and Algorithm.
    In IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), pages 4-11, 2006.


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