Institute for Reliable Computing
Head:
Prof. Dr. Siegfried M. Rump
PUBLICATIONS - SVEN-OLE VOIGT
- Daniel Kliem and Sven-Ole Voigt. An Asynchronous Bus Bridge for Partitioned Multi-SoC Architectures on FPGAs. In 23rd International Conference on Field Programmable Logic and Applications (FPL'13), Sep. 2013. (doi:10.1109/FPL.2013.6645569)
- Daniel Kliem and Sven-Ole Voigt. 2012 international conference on reconfigurable computing and fpgas, reconfig 2012, cancun, mexico, december 5-7, 2012. In ReConFig. IEEE, ISBN: 978-1-4673-2919-4, 2012. http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6410219.
- Daniel Kliem and Sven-Ole Voigt. A multi-core fpga-based soc architecture with domain segregation. In ReConFig, pages 1–7, 2012. (doi:10.1109/ReConFig.2012.6416764)
- M. Baesler, S. Voigt, and T. Teufel. FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers. International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011:13–19, 2011. (doi:10.1109/ReConFig.2011.41)
- M. Baesler, S. Voigt, and T. Teufel. A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA. International Journal of Reconfigurable Computing, 2010. (doi:10.1109/ICCD.2010.5647764)
- M. Baesler, S. Voigt, and T. Teufel. A Radix-10 Digit Recurrence Division Unit with a Constant Digit Selection Function. 28th IEEE International Conference on Computer Design (ICCD), pages 241–246, 2010. (doi:10.1109/ICCD.2010.5647764)
- M. Baesler, S. Voigt, and T. Teufel. An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier. Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL '10), pages 489–495, 2010. (doi:10.1109/FPL.2010.98)
- S. Voigt, M. Baesler, and T. Teufel. Dynamically reconfigurable dataflow architecture for high-performance digital signal processing. Journal of Systems Architecture, 56(11):561–576, 2010. Design Flows and System Architectures for Adaptive Computing on Reconfigurable Platforms. (doi:10.1016/j.sysarc.2010.07.010)
- S. Voigt. Dynamically Reconfigurable Dataflow Architecture for High-Performance Digital Signal Processing on Multi-FPGA Platforms. Dissertation. Shaker Verlag, 128 Seiten (Englisch), ISBN: 978-3-8322-7805-2, 2009. (hdl.handle.net/11420/8568)
- S. Voigt and T. Teufel. Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms. In Proceedings of the Sixteenth IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM '08, Stanford University, CA, 2008.
- S. Voigt and T. Teufel. Dynamically Reconfigurable Dataflow Architecture for High-Performance Digital Signal Processing on Multi-FPGA Platforms. In Proceedings of the IEEE Int. Conference on Field Programmable Logic and Applications (FPL2007), pages 633–637, 2007. (doi:10.1109/FPL.2007.4380734)